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stm32g0: use proper register for gpio peripheral clock sleep enable.

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Reviewed-by: Karl Palsson <karlp@tweak.net.au>
This commit is contained in:
Guillaume Revaillot 2019-08-28 18:04:02 +02:00 committed by Karl Palsson
parent 998e647dde
commit 8a1cfa8ceb
1 changed files with 6 additions and 6 deletions
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12
include/libopencm3/stm32/g0/rcc.h
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@ -678,12 +678,12 @@ enum rcc_periph_clken {
RCC_TIM1 = _REG_BIT(RCC_APBENR2_OFFSET, 11), RCC_TIM1 = _REG_BIT(RCC_APBENR2_OFFSET, 11),
RCC_SYSCFG = _REG_BIT(RCC_APBENR2_OFFSET, 0), RCC_SYSCFG = _REG_BIT(RCC_APBENR2_OFFSET, 0),
SCC_GPIOF = _REG_BIT(RCC_IOPENR_OFFSET, 5), SCC_GPIOF = _REG_BIT(RCC_IOPSMENR_OFFSET, 5),
SCC_GPIOE = _REG_BIT(RCC_IOPENR_OFFSET, 4), SCC_GPIOE = _REG_BIT(RCC_IOPSMENR_OFFSET, 4),
SCC_GPIOD = _REG_BIT(RCC_IOPENR_OFFSET, 3), SCC_GPIOD = _REG_BIT(RCC_IOPSMENR_OFFSET, 3),
SCC_GPIOC = _REG_BIT(RCC_IOPENR_OFFSET, 2), SCC_GPIOC = _REG_BIT(RCC_IOPSMENR_OFFSET, 2),
SCC_GPIOB = _REG_BIT(RCC_IOPENR_OFFSET, 1), SCC_GPIOB = _REG_BIT(RCC_IOPSMENR_OFFSET, 1),
SCC_GPIOA = _REG_BIT(RCC_IOPENR_OFFSET, 0), SCC_GPIOA = _REG_BIT(RCC_IOPSMENR_OFFSET, 0),
SCC_RNG = _REG_BIT(RCC_AHBSMENR_OFFSET, 18), SCC_RNG = _REG_BIT(RCC_AHBSMENR_OFFSET, 18),
SCC_AES = _REG_BIT(RCC_AHBSMENR_OFFSET, 16), SCC_AES = _REG_BIT(RCC_AHBSMENR_OFFSET, 16),