The adc peripheral on F30x is the same as F0, L0 and L4. In the reference
manuals, the following names are used.
F3: CFGR (no CFGR2)
F0 and L0: CFGR1 and CFGR2
L4: CFGR and CFGR2
Moving to a single consistent name, that's more likely to be inline with future
part numbers makes it much easier to extract common driver code for the
peripheral.
While all bit defines are moved to the CFGR1 style, core register definitions:
ADC_CFGR(adc) and ADCx_CFGR are kept to match the original register name in the
reference manual.
Fixes Github issue #548
The f3 adc has separate bits for end of conversion and end of sequence.
Support those fully, with the regular enable/disable irq methods, and
the flag checking methods.
Discovered in github bug: #493
This code was copied from the f4, and blindly modified to make it seem
to work. The f3 has separate flags for EOC and EOS, it doesn't use a
second bit to configure what the EOC bit does.
Consequently, update the documentation to correctly indicate that the
EOC bits are only set per conversion.
Discovered in github bug: #493
to remove variations, redundancies, add missing, fix errors. All c files
refer only to the dispatch style headers in /include/stm32. Those headers
#include memorymap.h and cm3/common.h. All references to
these are removed from the family specific headers. Ethernet untouched as
it appears incomplete.
Added dummy spi.c for F0/F3. Fix some doxygen anomalies.
According to RM0090, page 301, paragraph 11.13.12 Note. (For F4, for F1 and F3 is it in the corresponding manuals)
The JSQR are filled always ending at SQR4 ie for those lists we must set this list:
(A) -> JSQ4 = A,
(A,B) -> JSQ3 = A, JSQ4 = B,
(A,B,C) -> JSQ2 = A, JSQ3 = B, JSQ4 = C,
(A,B,C,D) -> JSQ1 = A, JSQ2 = B, JSQ3 = C, JSQ4 = D,
The readed values are in correct order, starting from JDR1:
(A) -> JDR1 = A,
(A,B) -> JDR1 = A, JDR2 = B,
(A,B,C) -> JDR1 = A, JDR2 = B, JDR3 = C,
(A,B,C,D) -> JDR1 = A, JDR2 = B, JDR3 = C, JDR4 = D,
