Drops all the l1 copies of this code, and automatically gains all the
following apis that weren't even available before:
void adc_set_clk_prescale(uint32_t prescaler);
void adc_set_resolution(uint32_t adc, uint32_t resolution);
void adc_enable_overrun_interrupt(uint32_t adc);
void adc_disable_overrun_interrupt(uint32_t adc);
bool adc_get_overrun_flag(uint32_t adc);
void adc_clear_overrun_flag(uint32_t adc);
bool adc_awd(uint32_t adc);
void adc_eoc_after_each(uint32_t adc);
void adc_eoc_after_group(uint32_t adc);
void adc_set_dma_continue(uint32_t adc);
void adc_set_dma_terminate(uint32_t adc);
Sampling time and sequence length, along with the vbat channel are
specific to the f4/f7, and can't be shared with the l1 and friends.
Pull them out to their own common file.
In adc_calibrate_async() we should only set the ADCAL bit and leave the rest alone.
While in the past there were only "rs" bits in this register, this is no
longer the case.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Make exti_get_flag_status and exti_reset_request use EXTI_RPR and EXTI_FPR if present instead of EXTI_PR.
This is less precise than offered by the RPR/FPR registers, but makes
for a consistent experience in the common API.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
EXTICR on stm32g0 is in exti registers range. Previous chips used to have that
gpio port exti mux configuration accessible via AFIO_EXTICR or SYSCFG_EXTICR.
Also, the new chip now use 8 bits coded value instead of previously 4 for the
extcr mux selection value (see AFIO/SYSCFG/EXTI_EXTICR_FIELDSIZE)
Let's define two helpers: EXTICR_SELECTION_REG (to get proper AFIO/SYSCFG/
EXTI_EXTICR register) and EXTICR_SELECTION_FIELDSIZE (to get proper AFIO/SYSCFG/
EXTI_EXTICR_FIELDSIZE value), and use it them exti_select_source to determine
exticr mux selection bits shift and mask.
flash_unlock_acr allows to unlock RUN_PD bit from FLASH_ACR register. Relock is done automatically
when writing 0 to RUN_PD, so no flash_lock_acr method.
the 2014q3 or later toolchains are now readily available, and we should
now just consider this a user problem. This gets us out of trying to
parse compiler help output and chasing our own tail.
Fixes https://github.com/libopencm3/libopencm3/issues/965
They were originally used to make sure that the doxygen was generated
correctly, but that style is no longer necessary.
There may be more peripherals that can be "cleaned" like this, but let's
do them one step at a time, as we work on that area.
See https://github.com/libopencm3/libopencm3/issues/873
Commentary describing this patch originally by zyp:
```
After looking further into it, I've concluded that my preliminary
analysis looks correct. The problem is that setting CNAK before
the SETUP complete event is received causes a race condition. The
SETUP callback is called when the SETUP packet event is received,
which means that setting CNAK from the callback is too early.
Originally the problem was that CNAK was set by ep_read() which is
called by the callback. #672 solved this by moving CNAK out of
ep_read() and calling it after the SETUP complete event is received
instead.
The regression by #785 is caused by the introduction of flow control
calls into the SETUP callback. They also set CNAK.
To solve this properly, I propose changing the event handling code
to only call the SETUP callback after the SETUP complete event is
received. Unfortunately, this implies that the callback can't call
ep_read() itself anymore, because the packet has to be read out of
the FIFO before the SETUP complete event arrives. This implies a
change of the API between the hardware drivers and _usbd_control_setup().
```
L1 (st_usbfs) works and passes tests as before change
F4 (dwc_otg_fs) works and now passes tests. (yay)
LM4f still compiles, and has had the same style of implementation as
st_usbfs, however has not been tested on any hardware.
Fixes https://github.com/libopencm3/libopencm3/issues/476
Sets USB_COUNTn_RX reg fields : bits <14:10> are NUM_BLOCK; bit 15 is BL_SIZE.
- When (size <= 62), BL_SIZE must be 0 and NUM_BLOCK set to (size / 2).
- When (size > 62), BL_SIZE must be 1 and NUM_BLOCK=((size / 32) - 1).
Previous code improperly set NUM_BLOCK and assumed the requested size was set.
Now, we use the next largest legal buffer size. Examples:
size BL_SIZE NUM_BLOCK => Actual bufsize
0 0 0 ??? (illegal !)
1 0 1 2
63 1 1 64
Algo is valid for F102, F103 and F0 devices (USB_FS peripheral).
In addition, the new usb_set_ep_rx_bufsize() function returns the actual
size set.
Tested-by: Karl Palsson <karlp@tweak.net.au>
LPUART1 needs BRR to be 256 times the normal value.
Doing this with 64 bit math would work, but that pulls in quite a lot of
code for every platform, even if they don't have LPUART.
A little bit of maths, thanks to zyp on irc, lets us keep it in 32bit,
provided people don't try and use > 16MBaud on LPUARTs
Originally tracked via https://github.com/libopencm3/libopencm3/pull/888
We extracted code out to the common files, but they weren't being
linked. This didn't matter in the past, as they were empty.
Fixes: 46d4103c stm32: flash: move wait_for_last to f2/f4 explicitly.
Fixes: https://github.com/libopencm3/libopencm3/issues/953
flash_clear_pgperr_flag is a name used on f247, which is actually most
analogous to the SIZERR bit on l4, (it's a parallelism error)
the bit being cleared originally in this function, PROGERR is a new bit,
and should have it's own name.
Add a function to handle the previously unhandled size/parallelism flag,
and rename the existing one to properly reflect it's new name.
This shows what is _actually_ different for f7. A couple of option
bits, and a renaming of bit 7 of the status register, from Program
Sequence Error to Erase Sequence Error.
We keep the separate implementation of wait_for_last_operation, to meet
the "suggestions" of the reference manual to insert a DSB instruction.
Keeping the renamed bit/functions also requires us to keep separate
implementations of the flag clearing functions
