I apparently based memorymap.h on previously written header without noticing
that g0 has only one apb despite a big hole in the memory space and addresses
matching usual apb1/apb2 split..
Regular rng peripheral, with one additional bit : clock error detection
apparently available on l4 chips). Curiously, Clock error detection is
_disabled_ when bit is set, but bit is cleared by default, so peripheral
/ clock error detection behaves like all other chips..
NB: RNG need proper rcc_ccicr_rngsel bits set to work, no clock is set by
default. Note also that on that chip fRNGCLK must be higher than fHCLK/32
You can't have two mainpage items, and the second was just being
ignored. This restores them, which makes the left side list longer,
which we may or may not like, but it's at least how it was documented to
be.
Functions that are already documented in the top level common api.h file
won't add any more documentation from later .c files. Keep docs for
part specifics, in the .h files where they're accessible to IDEs and
also the documentation generation, and drop all (including the redundant
ones) from the .c file.
the group defaults to the implicit container based on location, so drop
all the explicit @ingroups, less to maintain. Properly use /**@}*/ to
close all groups too, even though it mostly seems to have worked anyway.
Properly close all groups opened for files.
Make the names match the reference manuals properly, and add missing
names. Still a long way to go to unify across all families, but this is
at least closer.
here, it's a bit of a mess.. G0 flash controller does not really
match exsting feature split. IE it has instruction cache only ..
so, no flash_idcache.c as it. flash_common_f could be used, but
flash_unlock would not take care of option byte ?
prefetch, icache and lock is ok. I had no look at flash programming
or erase yet..
