SCB.CCR.STKALIGN enables the automatic aligning of the stack pointer to 8 bytes
on interrupt entry. Per ARM recommendations, and for AAPCS compliance, this
bit should be enabled at all times. ARMv6M has this hardcoded to 1. Cortex M3
has this broken in rev 0, optional (default off) in rev 1, and optional
(default on) in rev 2 and later. M4(f) has optional (default on) for all
revisions, M7 has hardcoded to 1.
See Section 2.3.3 in ARM document IHI0046B:
http://infocenter.arm.com/help/topic/com.arm.doc.ihi0046b/IHI0046B_ABI_Advisory_1.pdf
To ensure that all parts behave correctly, we make sure that we hardcode the
feature on, for all parts. While not _required_ for anything other than rev1
cm3, inserting it into the common reset handler ensures no-one gets any
surprises.
Fixes Github issue #516
The existing rcc_clock_setup_pll only allowed HSI as the clock source, even
though the existing clock structure contains pll source variables.
Check this value, and switch to the corresponding clock source, rather than
blindly assuming that we are tryign to operate from HSI.
(probably because the Ref Manual erroneously required it).
This has a naughty side-effect in that unrelated user data in the BD would be wiped.
Replaced this call by clearing the RTC registers to their default values.
Tested with ET-STAMP-STM32 to verify RTC starts from power-on and reset with expected behaviour.
This removes the shift from the defines, and includes them in the helper
function, making the code match the documentation, and following how the
rest of the library commonly operates.
Code using the existing defines will continue to work.
Basic helpers to at least support common configurations for the f401.
Original submission specified 5 wait states, but the reference manual and other
reviewers all believe that 2ws is sufficient for these modes.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
This makes it easier to read for most people, and makes it substantially
easier to review changes in the function signatures themselves at a
later date.
The f3 adc has separate bits for end of conversion and end of sequence.
Support those fully, with the regular enable/disable irq methods, and
the flag checking methods.
Discovered in github bug: #493
This code was copied from the f4, and blindly modified to make it seem
to work. The f3 has separate flags for EOC and EOS, it doesn't use a
second bit to configure what the EOC bit does.
Consequently, update the documentation to correctly indicate that the
EOC bits are only set per conversion.
Discovered in github bug: #493
Regression from 0cc0134f21b387a3a813feca1973c77587900ee2
When operating on registers in code that is common for both usb cores,
make sure to use the REBASE macros to operate on the correct peripheral.
Reported by: kuldeep
Fixes github issue: #495
The three existing usb drivers have no possible path that doesn't return
the object here, so I've left that comment, but it is plausible that
future drivers might have some reason that allows failing to init. We
should strive to avoid that though.
Fixes github issue: #494
The common case for SPI ports in master mode is that they are not
also running as Slaves some times. For these chips the SSOE bit must
be set (or NSS tied high). Since it is common for people to use a separate
GPIO to select remote slaves and they expect the master to always be the master
this sets that up by default.
-ggdb3 make slightly bigger .elf files, but allows gdb to understand
macros, which libopenocm3 uses somewhat extensively. Make this the
default, and pull it up to the common base makefile, so it can be easily
substituted.
This adds MCO source selection to some targets, and removes and standardizes
the mask/shift usage for all targets. For devices that support MCO2, this
supports only MCO1. No attempt has been made to extract MCO prescaler, which
is not available on all F1 and F3.
F0 should check the oscillator ready bits in the regular registers, just
like the docs claim, and just like every other stm32, rather than trying
to check for the interrupt flags.
Reported-by: n1b on irc
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
This commit implements the support for one interface to have multiple
altsettings. It also adds hook that user can use to perform actions
when the alsetting switch is performed by host.
Changes:
* For backward compatibility, placed a pointer instead of allocating memory for whole interface struct.
* Always execute callback (even if the current interface alternate-settings matches).
* Multiple configuration support.
Signed-off-by: Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
USB using control callbacks was broken since d6bad27735a77b8daa90ce72b843cf08ba78697d
Properly check if user usb control callback are registered,
while here make sure user_callback_set_config callback pointers are initialized to NULL.
Extends struct usb_endpoint_descriptor to make it possible to provide
the USB host with class-specific extensions to endpoint descriptors.
The approach taken, based on extra and extralen and removing the sizeof()
from USB_DT_ENDPOINT_SIZE, is identical to the approach used to add
class-specific extensions to interface descriptors. All libopencm3-examples
use the USB_DT_ENDPOINT_SIZE (rather than directly using sizeof) so there
should be no compatibility problems resulting from this change.
If there is no additional iface data then iface->extra is NULL and
iface->extralen is zero. Passing NULL to memcpy is undefined behaviour
even if the length of data to copy is zero. In other words a conforming
(debug) memcpy implementation is permitted to assert(dst && src) without
checking the value of n.
Add an extra branch to avoid this.
