Karl Palsson
|
40f3ac58fb
|
[l1] Add PWR register definitions
Just the include file.
|
2012-11-14 00:16:56 +00:00 |
|
Karl Palsson
|
259d4e5171
|
[l1] Add missing TIM5 bit from newer ref manual
|
2012-11-14 00:16:52 +00:00 |
|
Karl Palsson
|
72666a5b93
|
[l1] Add Flash Memory Controller Register defns for L1.
Also, some of the most basic essential helper functions.
|
2012-11-14 00:16:46 +00:00 |
|
Ken Sarkies
|
70746ccd67
|
Change to make L1 series fit with common files
|
2012-11-13 18:43:06 +10:30 |
|
Ken Sarkies
|
35c0863a75
|
Documentation updates
|
2012-11-12 21:44:52 +10:30 |
|
Karl Palsson
|
25acaa5878
|
Add usart support for L1.
Only tested with basic tx blocking, ie, the same example code as on
F2/F4, but the description of the block is almost identical.
|
2012-11-07 21:50:27 +00:00 |
|
Karl Palsson
|
4941286454
|
STM32L1 support, rebased onto upstream generalizations branch.
Working example again.
|
2012-11-07 21:50:27 +00:00 |
|
Karl Palsson
|
e4f84278f2
|
Add most of the rcc functions.
(Add the forgotten gpio.c file from before)
|
2012-11-07 21:50:27 +00:00 |
|
Karl Palsson
|
9aed64a19d
|
Finish RCC definitions => Working example!
|
2012-11-07 21:50:27 +00:00 |
|
Karl Palsson
|
8318384cf1
|
More progress towards L1 support.
Believe gpio is complete, but untested without finishing at least the
RCC defines.
RCC defines are a work in progress
|
2012-11-07 21:50:27 +00:00 |
|
Karl Palsson
|
2011941b55
|
Vectors and Memory Map for STM32L1 series
|
2012-11-07 21:50:27 +00:00 |
|