This is more in line with the actual hardware (u32 registers), and will still
work if PRIMASK or FAULTMASK ever have more than 1 bit defined.
The functions cm_is_masked_interrupts() and cm_is_masked_faults() are
unchanged, since returning 'bool' fits with the function naming.
Fixes most of github issue #475. What remains "unfixed" is the absence
of functions to simply 'get' the u32 value of PRIMASK and FAULTMASK registers.
The MPU RASR AP table has a duplicate entries for Privileged ReadOnly
and Usermode ReadOnly, in the source ARM document (Cortex M3 TRM)
Remove the duplicate here.
The MPU RASR Shareable, Bufferable and Cacheable bits are all individual
bits, and none of the existing defines appear to even match the ARM
documentation. Remove them, but leave the definitions of the bit
positions.
Reported by MightyPork on IRC
This adds the "volatile" keyword to all the inline assembly. gcc docs say "You can prevent an asm instruction from being deleted by writing the keyword volatile after the asm.". Testing (see comments of github issue #475) shows that indeed gcc can remove some inline asm, in at least this situation:
-multiple calls to cm_is_masked_interrupts() in the same scope/context
- -Os or -O2 optimization
This is problem because the value of PRIMASK could change between two calls to cm_is_masked_interrupts().
Adding the volatile keyword fixes this, and probably costs less than adding a full barrier (like adding "memory" to the clobber list).
These prototypes affect functions defined by application code. Only
the implementations in libopencm3 are supposed to be weak; the
functions in application code should definitely not be. Otherwise,
you'll end up with two weak symbols being linked together, and
it's luck as to which one the linker picks.
All the macro arguments that are user supplied, or potentially, wrap properly
in () as good practice.
Probably missed one or two, and a lot of them are possibly unnecessary, but
it's straightforward to just do it always.
Fixes github issue #321
The MPU is an implementation option available for both ARMv6-M and ARMv7-M.
Remove poorly merged code that attempted to include this only for cortex m0+.
Added doxygen, updated the definitions of the RBAR register, (though if you're
really using this periperhal, you should be looking at the ref man for further
information)
Reported-by: forrestv on irc.
While there might be other places that are missing this include, this
particular file is clearly missing them, and has resulted in a few separate bug
reports. Fix it right now, in the name of continuous improvement.
Fixes#310 and #427
When compiling with all warnings enabled, some defines can lead to
warning due to missing unsigned type suffix:
warning: integer overflow in expression [-Woverflow]
This fix should not affected behavior at all, since calculation with
such overflows lead to the same actual address when writing to that
location. However, it makes the warning disappear and also defines
the right data type for a memory location.
ITM Stimulus ports need to be accessible with different sizes
The amount of data written out is determined by the size of the write.
Writing a full 32 bit value when you only need 8 for printf() style
substantially reduces the available bandwidth of the SWO
Note: this is an API change for doing 32bit writes.
Old:
ITM_STIM[stimulus_port] = value
New:
ITM_STIM32(stimulus_port) = value
This api is much more in common with some of the other registers that
behave this way. As there's very little (if any) code already using
this API, it's a good time to fix it permanently.
Remove misleading ITM register definitions
ITM_SSPSR is the supported parallel trace size, in _bits_
ITM_CSPSR is in _bits_ as well. There's really no advantage in even
having these sorts of definitions in libopencm3, as these settings are
normally controlled from the debugger side, not the target itself.
Lock and lock status register definitions were added, as per ARM:
"For ARMv7-M, the component ID registers are required for the ROM table,
and the CoreSight management lock access mechanism is defined for the
DWT, ITM, FPB and TPIU blocks."
The direct access definitions to the SHPR1 SHPR2 and SHPR3 were simply
wrong, and though a handy macro for directly reaching any priority field
was provided, the definitions of the fields assumed direct access to the
registers.
Provide field definitions that match the handy macro, and correct the
direct access definitions for people wishing to use them.
We should not add compiler extensions, it is not our job. We are not a
selfcontained project as kernel is so we should not introduce things
like this.
If we need to add some abstraction for this in the future to support
compilers doing these things differently then we will do that the same
way we dealt with the depricated attribute.
In places where we were defining memory mapped peripheral buffers we
were using directly a cast to "volatile int_type *". For consistency we
should use dereferenced accessor like: &MMIO32(address)
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.
We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
only contain one statement. Otherwise it is easy to introduce an
error.
Checkpatch needs to be adapted to reflect those changes.
Adding this attribute allows to avoid warnings issued by GCC in cases
when 'scb_reset_system' is used as a last call in a function with
"noreturn" attribute set(usually reset handler of some sorts)
This commit add a structure definition that represents the stack frame
layout as it is upon entering exception handler. This is useful when
one wants to alter the exception return address, or get information
about registers state saved by the CPU.
