19 Commits

Author SHA1 Message Date
Karl Palsson
2b54119b78 cm3: scs: drop all duplicate information
Keeps the best version of the documentation.

Fixes: https://github.com/libopencm3/libopencm3/pull/269
2019-10-18 22:38:16 +00:00
Karl Palsson
833da4b672 cm3: extract SCB SHPR to the SCB world it belongs to
Pull out the duplicate into the right file, keeping the newly fixed
version.
2019-10-18 22:33:23 +00:00
Karl Palsson
3ebd71b464 cm3: extract Coresight LSR/LAR definitions
Use a single point of definition for the offset, and add it where it was
missing.
2019-10-18 22:29:13 +00:00
Matt Anderson
d8579dde95 CortexM0: IPR and SHPR are only word addressable
For ARMv6M, the IPR and SHPR registers are accessible only when
adddressed with a 32bit word read or write.

Currently in libopencm3 all NVIC interrupt priority register accesses
are made using an 8bit read or write, which results in the hardware
ignoring the write or always returning 0 on read.

Address this by introducing NVIC_IPR32() and SCS_SHPR32() macro and
conditional implementation of nvic_set_priority when building for
cortex-m0.

See ARMv6M developer documentation:
IPR: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/Cihgjeed.html
SHPR: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/CIAGECDD.html
2019-10-17 21:26:13 +00:00
Karl Palsson
cae295ee2c doc: cm3/scb+scs: turn on existing documentation
Lots of registers were already documented extensively.  Turn it all in
doxygen with groups and the right syntax.
2018-09-09 15:27:41 +00:00
Karl Palsson
1ad2cda496 doc: add all cm3 headers to doxygen.
Just get them all included as they are.  Gets them grouped up and
visible so we can start clarifying the rest of their docs.
2018-09-09 15:27:41 +00:00
Karl Palsson
0c91dbf57e cm3: scs: drop (superseded) helper macros for systick
These are superseded by cm3/systick.h and the functions there.

Reported originally under: https://github.com/libopencm3/libopencm3/issues/125
2018-08-21 21:20:57 +00:00
Karl Palsson
cfe514913f cm3: scs: drop (superseded) dwt macros
They are all superseded by dwt.h, and the function dwt_enable_cycle_counter

Fixes https://github.com/libopencm3/libopencm3/issues/125

(But only for the cycle count enabling)
2018-08-21 21:20:51 +00:00
Karl Palsson
c72f3d588a Surround all macro parameters with ()
All the macro arguments that are user supplied, or potentially, wrap properly
in () as good practice.

Probably missed one or two, and a lot of them are possibly unnecessary, but
it's straightforward to just do it always.

Fixes github issue #321
2015-10-14 22:15:15 +00:00
Karl Palsson
ec9fc5c122 [swo] Add/Update definitions necessary for SWO to work
ITM Stimulus ports need to be accessible with different sizes

The amount of data written out is determined by the size of the write.
Writing a full 32 bit value when you only need 8 for printf() style
substantially reduces the available bandwidth of the SWO

Note: this is an API change for doing 32bit writes.
Old:
    ITM_STIM[stimulus_port] = value
New:
    ITM_STIM32(stimulus_port) = value

This api is much more in common with some of the other registers that
behave this way.  As there's very little (if any) code already using
this API, it's a good time to fix it permanently.

Remove misleading ITM register definitions

ITM_SSPSR is the supported parallel trace size, in _bits_
ITM_CSPSR is in _bits_ as well.  There's really no advantage in even
having these sorts of definitions in libopencm3, as these settings are
normally controlled from the debugger side, not the target itself.

Lock and lock status register definitions were added, as per ARM:
  "For ARMv7-M, the component ID registers are required for the ROM table,
   and the CoreSight management lock access mechanism is defined for the
   DWT, ITM, FPB and TPIU blocks."
2013-11-21 16:21:38 +00:00
BuFran
efc2489d2c [Stylecheck] Code cleaned to current stylecheck script 2013-08-22 17:18:41 -07:00
Piotr Esden-Tempski
169dbd6c08 Dropped raw option on github file archive links. 2013-06-13 11:26:16 -07:00
Piotr Esden-Tempski
e4a86e269e Replaced goo.gl links with links to our new file archive at github.
https://github.com/libopencm3/libopencm3-archive
2013-06-13 11:20:04 -07:00
Piotr Esden-Tempski
7df63fcae0 First coarse run to fix coding style in locm3.
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.

We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
  only contain one statement. Otherwise it is easy to introduce an
  error.

Checkpatch needs to be adapted to reflect those changes.
2013-06-12 18:22:56 -07:00
TitanMKD
8d97dbc7c3 Work on scs.h register and also nvic.h.
ARM Interrupt API (see nvic.h).
ARM SysTick API (see systick.h).
Example using both Interrupt and SysTick and blink LED1/2/3 see systickdemo.c.
2012-06-09 18:27:42 +02:00
Piotr Esden-Tempski
43561de329 License change of the library to LGPL, version 3 or later.
Agreed to by all the significant contributors to the library.
2012-03-02 14:44:49 -08:00
Gareth McMullin
f0a1282d42 Added ITM and TPIU register definitions. 2011-02-17 21:38:38 +13:00
Uwe Hermann
447c333cec Minor cosmetics, whitespace. 2011-02-09 01:06:43 +01:00
Gareth McMullin
4954b4c006 Added ARMv7-M Core Debug (SCS) register definitions. 2011-02-08 19:26:38 +13:00