Add basically what's needed to have some minimal but usefull subset of
function for a timer: irqs, compare, period, out polarity, enable/disable
and start.
doxygen really wants the @defgroup _and_ the @addtogroup to both have
the full name, matching identically, to avoid all warnings.
Standardize on the "CAPS_PERIPH peripheral API" style.
The leading - makes it rather inconsistent with the majority of other
projects around the world. Use the form everyone else uses.
To solve this, properly pass prefix to inner makes as was always
intended.
Fixes: https://github.com/libopencm3/libopencm3/issues/1058
48Mhz has no purpose other than to be a naiive method of haivng working
USB. 120MHz never had any purpose, other than to match the f2 code it
was copied from. Drop them both. Remaining configs are all max speeds
for various F4 parts. Lower speeds are all custom
Some families had partially moved to peripheral api, and others were
only documenting common code, but not specific code. Delete dummy .c
files, and check that all specific apis are also being documented, not
just common apis.
Sampling time and sequence length, along with the vbat channel are
specific to the f4/f7, and can't be shared with the l1 and friends.
Pull them out to their own common file.
They were originally used to make sure that the doxygen was generated
correctly, but that style is no longer necessary.
There may be more peripherals that can be "cleaned" like this, but let's
do them one step at a time, as we work on that area.
We extracted code out to the common files, but they weren't being
linked. This didn't matter in the past, as they were empty.
Fixes: 46d4103c stm32: flash: move wait_for_last to f2/f4 explicitly.
Fixes: https://github.com/libopencm3/libopencm3/issues/953
This shows what is _actually_ different for f7. A couple of option
bits, and a renaming of bit 7 of the status register, from Program
Sequence Error to Erase Sequence Error.
We keep the separate implementation of wait_for_last_operation, to meet
the "suggestions" of the reference manual to insert a DSB instruction.
Keeping the renamed bit/functions also requires us to keep separate
implementations of the flag clearing functions
Turns out, there's lots of common code for flash. Pull up prefetch
on/off to start with, as there's only a single bit name different.
Pull up the definitions of common API functions too, starting with
flash_set_ws. Even if the implementations are different, things that
meant to be the same, should be defined centrally.
- Change .power_save to .voltage_scale, a pwr_vos_scale enum
- Enable pwr clock before setting VOS scale
- Fix flash wait states
- Make flash_set_ws more robust
Only applied to STM32 doc trees at present.
Instead of declaring a group for "STM32blah" in the doc-blah.h files,
and then trying to put all the common+specific peripheral code into
those groups, (which is what led to the stub doxygen holder empty .c
files) Just use a standard name like "Peripheral APIS" and place
everything into that.
Demonstrated by converting ADC and USART peripherals, which is
definitely not complete, but it shows how to make things less magical,
and less prone to copy/paste errors. Now, you can copy/paste and it
will do the right thing, because everyone uses the same group names.
This is also how to unify the mix of "STM32blah->Periphblah" and _also_
the dangling "periph_file" modules in doxygen, it merges them together
properly, as they're intended to be really.
On some targets these weren't even being referenced, on others they
were, in all cases they were empty and contributed no value.
They _actually_ served to declare groupings for doxygen, but we can do
that in a different manner, without having to have dummy files around.
split spi stuff in three part:
- v1 : basic spi peripheral
- v1_frf : v1 spi with frf mode additional bit in spi_cr2 / spi_sr
- v2 : spi with variable datasize, fifo and other fancy stuff.
v1 maps to f1 chips
v1_frf to f2, f4 and l0,l1
v2 to f0, f3 and l4
This breaks spi_master_init API for v2 devices : function prototype from
common spi header used to be abused, with DFF bit reused for CRCL bit.
New v2 spi_master_init does not handle anymore CRCL bits, as it does not
usually mess with other crc configuration.
Instead of every "simple" target having their own duplicate file with
all the section mappings, just provide a single, simple,
"cortex-m-generic.ld" that works with our startup code and any simple
rom/ram system. This also drops the pointless copying of files all over
the place. Using -L flags properly is sufficient, and the standard file
is now in the root of the library already.
The stm32fx07 is common DesignWare IP, used in both STM32 and EFM32 chips.
Rename the files to make this more clear, and easier to use in other
targets.
rcc_osc_bypass_enable and rcc_osc_bypass_disable have been copy/pasted
around for the last time! There's a compile bit to check for L0/L1, but
otherwise this is just code duplication for no gain.
