Clearing a single bit in DMA_CCR, then immediately writing a 0 over the
entire register is completely redundant on the F1, F3 and L1 DMA
peripherals. (Unlike the F2 & F4 DMA Peripheral, where this is
required)
Add an example using the RTC to help with a lower power design. This is
a sister example to the existing "button-irq-printf", which is
functionally identical, but uses far less power.
There's more tricks that can be done to lower the power even further,
but this shows a few of the early steps that can be done, using the RTC
wakeup instead of a timer.
Add the register definitions and some of the most basic helper functions
for the new style BCD RTC module found on the F2, F4, L1, F3 and F0.
This tries to keep as close to HACKING_COMMON_DOC as possible, while
maintaining sane names.
Code added for L1 to support the PWR Control block didn't properly
follow the HACKING_COMMON_DOC guidelines. The naming was wrong, and
some headers were missing. This commit has no functional changes, it
only addresses the style and structure problems.
Earlier additions to the L1 support were not correctly using linux
coding guidelines as specified in /HACKING.
Some examples were also missing license information.
Updated the documentation so that it appears in all families
Also added it to the L1 area, but is untested. An addition to the memorymap
allows commonality and a #ifdef added to the spi_common_all code to
exclude the case of SPI3 for L1 and F0 as SPI3 doesn't exist in those.
An rcc dispatch header was added to remove same code from the spi header.
In the header:
- Fix DMA_SxCR_CT: change shift from 18 to 19
For use with the convenience functions:
- Added DMA_SxCR_CHSEL generic values
- Added DMA_STREAM - generic values
- Added dma_if_offset - rather than separating out LISR and HISR
- Added masks
- Added dma_disable_double_buffer_mode()
This has only been tested functionally with basic timers, and basic operations.
Advanced timer support has been #ifdefed to compile, but this probably needs more testing.
Despite the L1 being a low power device, my initial focus is on making
it basically compatible with existing devices.
To that end, provide clock setup helper routines that configure it for maximum performance,
allowing some similar clock speeds to F1 devices to help with testing. This requires adding
the power chipset routines to set the voltage range.
Clock setup style is similar to the F4 code, which seems nicer than the overflow of different
routines used on the F1 code.
NOTE: Both the F4 existing pwr code, and this code don't actually include the f1 core power
code, even though it should be compatible
