The existing rcc_clock_setup_pll only allowed HSI as the clock source, even
though the existing clock structure contains pll source variables.
Check this value, and switch to the corresponding clock source, rather than
blindly assuming that we are tryign to operate from HSI.
Rename rcc_ppre1_frequency and rcc_ppre2_frequency to rcc_apb1_frequency and rcc_apb2_frequency
Also add rcc_ahb_frequency (although it is not set correctly in all cases) which will be fixed by
the rcc commits later. Also fixup the only use in the library of these variables, the USART code.
And fix the typos that resulted
Make l1 generic too
to remove variations, redundancies, add missing, fix errors. All c files
refer only to the dispatch style headers in /include/stm32. Those headers
#include memorymap.h and cm3/common.h. All references to
these are removed from the family specific headers. Ethernet untouched as
it appears incomplete.
Added dummy spi.c for F0/F3. Fix some doxygen anomalies.
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.
We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
only contain one statement. Otherwise it is easy to introduce an
error.
Checkpatch needs to be adapted to reflect those changes.
According to the reference manual, you are _forbidden_ from writing 00 to the
VOS[1:0] bits in PWR_CR. Writing a 00 is automatically turned into range 2,
or, 10. Attempting to then |= the bits for range 1 (01) results in the final
result of choosing voltage range 3 (11). This has fairly catastrophic effects
if you then attempt to switch to PLL clock at 32Mhz.
Oddly, the existing code was working fine on STM32L151C6 revision W, but
failing with revision V silicon. Regardless, the existing code was wrong and
not following the reference manual.
Further, attempting to change any power voltage range settings without the RCC
enabled will have no effect, so all the higher level helper routines
have added peripheral enable lines before attempting to set the range.
This switch to HSI was an attempt to run the setup code faster. However,
there's no real need for this, and it just confuses things by switching first
to one clock, and then to another. Just keep running on the existing clock
until switching to the clock actually chosen by the user's arguments.
Add an example using the RTC to help with a lower power design. This is
a sister example to the existing "button-irq-printf", which is
functionally identical, but uses far less power.
There's more tricks that can be done to lower the power even further,
but this shows a few of the early steps that can be done, using the RTC
wakeup instead of a timer.
Code added for L1 to support the PWR Control block didn't properly
follow the HACKING_COMMON_DOC guidelines. The naming was wrong, and
some headers were missing. This commit has no functional changes, it
only addresses the style and structure problems.
Earlier additions to the L1 support were not correctly using linux
coding guidelines as specified in /HACKING.
Some examples were also missing license information.
Despite the L1 being a low power device, my initial focus is on making
it basically compatible with existing devices.
To that end, provide clock setup helper routines that configure it for maximum performance,
allowing some similar clock speeds to F1 devices to help with testing. This requires adding
the power chipset routines to set the voltage range.
Clock setup style is similar to the F4 code, which seems nicer than the overflow of different
routines used on the F1 code.
NOTE: Both the F4 existing pwr code, and this code don't actually include the f1 core power
code, even though it should be compatible
