5 Commits

Author	SHA1	Message	Date
Onno Kortmann	fe6b542357	STM32F0: Correctly clear pll source bits.	2013-12-16 19:42:21 +00:00
Onno Kortmann	f622437cfb	STM32F0: Fix PLL multiplication factor for 48MHz setup ... It was set to overclocking configuration!	2013-12-16 19:37:07 +00:00
Onno Kortmann	868d65d872	STM32F0: Turn on PLL clock source when asked to ... The STM32F05xxx/06xxx manual describes on p.98 (Sec 7.4.1) the RCC_CR register, on which it says that bit 24 is the PLLON bit which has to be enabled before using the PLL. This causes the PLL to be enabled with rcc_osc_on(PLL).	2013-12-16 19:37:06 +00:00
BuFran	81982916e2	[Doxygen] Add complete documentation page to STM32F0	2013-08-22 17:18:42 -07:00
BuFran	18c4d299c1	[STM32F0] Add preliminary support for the family	2013-08-22 17:18:35 -07:00