This was inspired by an Arch Linux provided ARM GCC 5.3.0 bug:
It gave an
"internal compiler error: in expand_expr_addr_expr_1, at expr.c:7736"
with the array version of the desig_get_unique_id.
While I was at it, fixed:
- a potential alignment issue with casting uint8_t* buf to uint32_t*
- a funny static in the string definition that does nothing (given const)
This reverts commit aa5e108553ace3079c6087dec796b9e58fe45fa4.
This commit was not meant to land yet, it should have gone for review, and
doesn't yet include all the parts it should touch.
replace bulky hardcoded wait for set and wait for clear with a single asynch
routine. Leave the blocking routines in for compatibility at this point.
NOUP: should be added to other rcc.c files too.
L4 and F3 actually have the same bits to write in the same order, but F3 hides
the name of the deep power down bit. Keep the like that for now, but there's a
standard API for enabling and disabling the regulator.
Now that the big pieces of the adc-v2 common files are in place, start
including l0 in the builds. This includes only the very very basic core v2
peripheral functions, and the very basic definitions.
The adc v2 periph has the same register map, but comes in two flavours, one
supporting injected channels, more watchdogs, per channel sampling times and
so on, and one "simple" version.
Pull up the f3 and f0 portions into the appropriate files, after comparing with
L0 and L4 reference manuals, even if those are not fully landed yet.
The f0, f30x and l0 have a very similar "v2" adc peripheral.
Start extracting out some of the common code, and fix the glaring bug in
adc_power_down that was affecting them both.
This is not intended to be a fully comprehensive extraction, just the first
easy steps.
The adc peripheral on F30x is the same as F0, L0 and L4. In the reference
manuals, the following names are used.
F3: CFGR (no CFGR2)
F0 and L0: CFGR1 and CFGR2
L4: CFGR and CFGR2
Moving to a single consistent name, that's more likely to be inline with future
part numbers makes it much easier to extract common driver code for the
peripheral.
While all bit defines are moved to the CFGR1 style, core register definitions:
ADC_CFGR(adc) and ADCx_CFGR are kept to match the original register name in the
reference manual.
Fixes Github issue #548
There are as many SMPRx registers are needed for channels supported, and on all
other families, the field definitions are just ADC_SMPR_SMP_XXX. For
consistency, and to avoid any confusion or duplication, use the same style here
too. Drop silly unused per channel definitions that have no purpose.
At least temp sensor, vrefint and vbat/vlcd should have consistent names and
consistent doxygen.
Dropped channel definitions that are the same as the raw number.
It's not used anywhere, and if this sort of api becomes needed, it can be
designed cleanly and finished.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
This is more in line with the actual hardware (u32 registers), and will still
work if PRIMASK or FAULTMASK ever have more than 1 bit defined.
The functions cm_is_masked_interrupts() and cm_is_masked_faults() are
unchanged, since returning 'bool' fits with the function naming.
Fixes most of github issue #475. What remains "unfixed" is the absence
of functions to simply 'get' the u32 value of PRIMASK and FAULTMASK registers.
The MPU RASR AP table has a duplicate entries for Privileged ReadOnly
and Usermode ReadOnly, in the source ARM document (Cortex M3 TRM)
Remove the duplicate here.
The MPU RASR Shareable, Bufferable and Cacheable bits are all individual
bits, and none of the existing defines appear to even match the ARM
documentation. Remove them, but leave the definitions of the bit
positions.
Reported by MightyPork on IRC
Original commits, while appearing clean and tidy, hadn't even been
compile tested. Trust no-one. Not even Scully.
Fixes: 770878e7b4ac12513e121e087261ca0972ba04e6
Fixes: 86d20ef00c00a14d7a4f0b834b9b608b2dd3638a
Fixes: 05ff0df32226dc28e22b98afde07bb886af9ddc9
This adds the "volatile" keyword to all the inline assembly. gcc docs say "You can prevent an asm instruction from being deleted by writing the keyword volatile after the asm.". Testing (see comments of github issue #475) shows that indeed gcc can remove some inline asm, in at least this situation:
-multiple calls to cm_is_masked_interrupts() in the same scope/context
- -Os or -O2 optimization
This is problem because the value of PRIMASK could change between two calls to cm_is_masked_interrupts().
Adding the volatile keyword fixes this, and probably costs less than adding a full barrier (like adding "memory" to the clobber list).
