- Makefiles now include building f3 src directory.
- Gpio support added. gpio_common_f24 changed to support also f3.
- f3 still not compiling, but f2 compile not broken (probably also f4).
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.
We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
only contain one statement. Otherwise it is easy to introduce an
error.
Checkpatch needs to be adapted to reflect those changes.
Added hash processor register definitions and main functions. Hash
processor is supported in stm32f21, stm32f41 and stm32f43 and can be
used to calculate Md5 and Sha1.
F2 and F4 have a common section to deal with the options register (TIM2 and TIM5 only)
L1 has been made common with timer_common_all as its options register has very different settings to F2/F4. Code is in the L1/timer.c L1/timer.h files
Note that F3 and F05 timers should fit into this scheme, with F3 having additional features.
Bundled with this is L1/pwr.h to change a documentation setting
Also all the Doxyfiles have added "ENABLE_PREPROCESSING = NO" to fix a problem introduced by commit 118.
(prevents inclusion and also issues warning)
Changes to some source files to remove references to common headers.
Changes to rng.h to make guard symbols the same in f2 and f4.
to remove errors, duplications and inconsistencies.
File lib/stm32/f1/pwr.c - all code removed as it duplicates that in common/pwr_common.c
Remaining changes do not affect code. Compiles OK.
TODO efm32 has no code so generates no modules
TODO F2 needs pwr.c
TODO L1 needs dma.h and dma.c
Most peripheral headers simply include <libopencm3/stm32/memorymap.h>
which, like the rest of libopencm3 requires the correct compiler define
flag to be set. A few peripherals were directly including the platform
include, libopencm3/stm32/xx/memorymap.h, and in some of those cases it
wasn't even correctly including the correct platform. (Likely the
result of copy/paste errors)
These direct includes have been eliminated
Add the register definitions and some of the most basic helper functions
for the new style BCD RTC module found on the F2, F4, L1, F3 and F0.
This tries to keep as close to HACKING_COMMON_DOC as possible, while
maintaining sane names.
Updated the documentation so that it appears in all families
Also added it to the L1 area, but is untested. An addition to the memorymap
allows commonality and a #ifdef added to the spi_common_all code to
exclude the case of SPI3 for L1 and F0 as SPI3 doesn't exist in those.
An rcc dispatch header was added to remove same code from the spi header.
In the header:
- Fix DMA_SxCR_CT: change shift from 18 to 19
For use with the convenience functions:
- Added DMA_SxCR_CHSEL generic values
- Added DMA_STREAM - generic values
- Added dma_if_offset - rather than separating out LISR and HISR
- Added masks
- Added dma_disable_double_buffer_mode()
these register definitions are common to all cortex mcus. some of the
registers might not be implemented everywhere (especially the floating
point registers), but defining them does no harm.
this modification does not result in any changes in the example
binaries.
the cortex generic interrupts get moved to lib/cm3/vector.c, the
platorms' individual irq names, initialization and handler prototypes go
to platoform specific irq.h files.
as the vector.c file heavily depends on platoform specific headers, it
can't be built once-and-for-all in lib/cm3/, so there are inclusion
stubs in the various architecture dirs; this might be better solved with
Makefile / include path handling.
one particular file is lib/lpc43xx/vector.c; that platform's
initialization code contains an additional section to copy everything
from flash to ram (which probably performs better there). that code
still resides in the inclusion stub, and gets mashed in using defines.
would need a cleaner implementation together with the Makefile solution.
this commit contains some files of the upcoming efm32 branch, from which
it was cherry-picked.
the .bin files produced from before and after this commit only differ in
lpc43xx, where the startup sequence was subtly modified.
New doc directory with config files and generated html, LaTeX/pdf.
Makefile provided for autogeneration and explanatory README.
The project structure is hostile to doxygen, which can't cope with functions
of the same name. Doxygen is run for each family separately, and separately
for LaTeX generation. Customized layout files sort of "integrate" HTML, and
separate pdfs are generated for each family. Not ideal but seems the best
solution until doxygen changes, if at all.
This was also fixed in ac29b654a992a4855626fc0b92874d3847914f85 in a
different way. I think the mask definition should be left with 1s
indicating the bits of interest.
See also 87ea496ca768d18e51d8654cbad9cb261a881b1b.
This reverts commit 2433f17e7341d6afcda24d395d0b93c50a37b7b1.
- Rename SPI_CR2_FRF_TI to SPI_CR2_FRF_TI_MODE to match datasheet.
- Rename SPI_CR2_FRF_MOTOROLA to SPI_CR2_FRF_MOTOROLA_MODE (see above).
- Fix SPI_CR2_FRF_MOTOROLA_MODE bit definition, must be (0 << 4).
- Change SPI_SR_RXNE to SPI_SR_TIFRFE; this was probably a copy-paste
error. Also, the bit definition is (1 << 8).
