I2C3 is on many parts, but wasn't properly supported with the register
definitions. Declare them centrally, just depending on the memorymap
defining them. On some parts, the rcc bits were defined, but not the
base registers.
Fixes: https://github.com/libopencm3/libopencm3/issues/820
Just a small typo I came across while trying to get MCO to work on my board.
The define is not used in any other files as far as I can tell, but of
course applications might break if they use the misspelt variant.
flash_clear_pgperr_flag is a name used on f247, which is actually most
analogous to the SIZERR bit on l4, (it's a parallelism error)
the bit being cleared originally in this function, PROGERR is a new bit,
and should have it's own name.
Add a function to handle the previously unhandled size/parallelism flag,
and rename the existing one to properly reflect it's new name.
This shows what is _actually_ different for f7. A couple of option
bits, and a renaming of bit 7 of the status register, from Program
Sequence Error to Erase Sequence Error.
We keep the separate implementation of wait_for_last_operation, to meet
the "suggestions" of the reference manual to insert a DSB instruction.
Keeping the renamed bit/functions also requires us to keep separate
implementations of the flag clearing functions
Move the last few register defines back to their relevant headers, add
doxygen and groups. While these registers _were_ "common" they were the
_only_ common things, so it's simpler for future work (merging f7 with
f2/4) to move them back separately.
F3's flash interface is actually quite different, don't try and force
sharing code that isn't really related. The "PGERR" is a very different
bit than the parallelism error that f2/4/7 have.
l4 is pages, not sectors, so update apis to be consistent. (other
families use page/sector as defined in the reference manual)
Make sure that pages on the second bank can also be erased. Use the
same style in use for f2/4/7 for sector numbers across banks.
All the "f" type flash parts have an EOP flag, even if it's in different
bit positions. Add a header for this common functionality, and move
it's implementation to the existing common file.
Turns out, there's lots of common code for flash. Pull up prefetch
on/off to start with, as there's only a single bit name different.
Pull up the definitions of common API functions too, starting with
flash_set_ws. Even if the implementations are different, things that
meant to be the same, should be defined centrally.
- Change .power_save to .voltage_scale, a pwr_vos_scale enum
- Enable pwr clock before setting VOS scale
- Fix flash wait states
- Make flash_set_ws more robust
The LTDC include file was defined with combined bit
semantics and bit position. As a result instead of
LTDC_GCR_VSPOL which is the bit which defines vertical
sync polarity, this had been defined to be
LTDC_GCR_VSPOL_LOW (0) and LTDC_GCR_VSPOL_HIGH (non zero).
This sort of define makes it impossible to know ahead of
time what operation would set or reset the bit (some are
negative logic, others are postive logic, so affirmative
defines could mean either "set the bit" or "reset the bit"
I've added the non-semantic bit define so that it is clear
in my code if the bit is being set or reset.
Discussion took place at https://github.com/libopencm3/libopencm3/pull/889
We didn't actually mark it deprecated very well, but it was
non-functional, and simply a poorly implemented wrapper for
rcc_periph_reset_pulse() anyway.
It's now been obsoleted in the examples for more than a year, and it's
time to kill it outright.
Fixes: https://github.com/libopencm3/libopencm3/issues/709
Only applied to STM32 doc trees at present.
Instead of declaring a group for "STM32blah" in the doc-blah.h files,
and then trying to put all the common+specific peripheral code into
those groups, (which is what led to the stub doxygen holder empty .c
files) Just use a standard name like "Peripheral APIS" and place
everything into that.
Demonstrated by converting ADC and USART peripherals, which is
definitely not complete, but it shows how to make things less magical,
and less prone to copy/paste errors. Now, you can copy/paste and it
will do the right thing, because everyone uses the same group names.
This is also how to unify the mix of "STM32blah->Periphblah" and _also_
the dangling "periph_file" modules in doxygen, it merges them together
properly, as they're intended to be really.
Deprecate the old routine and make a new one that actually handles HSI
and HSE properly, and includes the predivider and the usb divider
settings as well.
STM32L0 uses the same DMA peripheral as STM32F0, F1, L1 and others
with some differences. Those are mostly in the number of supported
controllers and channels.
This patch enables the basic support with no attempt to only expose
the available controllers / channels.
For more information see the ST Application Note AN2548.
Signed-off-by: Martin Sivak <mars@montik.net>
split spi stuff in three part:
- v1 : basic spi peripheral
- v1_frf : v1 spi with frf mode additional bit in spi_cr2 / spi_sr
- v2 : spi with variable datasize, fifo and other fancy stuff.
v1 maps to f1 chips
v1_frf to f2, f4 and l0,l1
v2 to f0, f3 and l4
This breaks spi_master_init API for v2 devices : function prototype from
common spi header used to be abused, with DFF bit reused for CRCL bit.
New v2 spi_master_init does not handle anymore CRCL bits, as it does not
usually mess with other crc configuration.
