This removes the shift from the defines, and includes them in the helper
function, making the code match the documentation, and following how the
rest of the library commonly operates.
Code using the existing defines will continue to work.
Basic helpers to at least support common configurations for the f401.
Original submission specified 5 wait states, but the reference manual and other
reviewers all believe that 2ws is sufficient for these modes.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
The f3 adc has separate bits for end of conversion and end of sequence.
Support those fully, with the regular enable/disable irq methods, and
the flag checking methods.
Discovered in github bug: #493
This code was copied from the f4, and blindly modified to make it seem
to work. The f3 has separate flags for EOC and EOS, it doesn't use a
second bit to configure what the EOC bit does.
Consequently, update the documentation to correctly indicate that the
EOC bits are only set per conversion.
Discovered in github bug: #493
The common case for SPI ports in master mode is that they are not
also running as Slaves some times. For these chips the SSOE bit must
be set (or NSS tied high). Since it is common for people to use a separate
GPIO to select remote slaves and they expect the master to always be the master
this sets that up by default.
-ggdb3 make slightly bigger .elf files, but allows gdb to understand
macros, which libopenocm3 uses somewhat extensively. Make this the
default, and pull it up to the common base makefile, so it can be easily
substituted.
This adds MCO source selection to some targets, and removes and standardizes
the mask/shift usage for all targets. For devices that support MCO2, this
supports only MCO1. No attempt has been made to extract MCO prescaler, which
is not available on all F1 and F3.
F0 should check the oscillator ready bits in the regular registers, just
like the docs claim, and just like every other stm32, rather than trying
to check for the interrupt flags.
Reported-by: n1b on irc
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Rename rcc_ppre1_frequency and rcc_ppre2_frequency to rcc_apb1_frequency and rcc_apb2_frequency
Also add rcc_ahb_frequency (although it is not set correctly in all cases) which will be fixed by
the rcc commits later. Also fixup the only use in the library of these variables, the USART code.
And fix the typos that resulted
Make l1 generic too
Pulls out duplicate calls from f0/rcc.c and uses the common version which
also means that f0 can use rcc_peripheral_enable() now which is in common
but not the old rcc versions.
Tested with a miniblink example on the l053 discovery board.
Only register definitions at this stage, no helpers.
Register definitions from RM0367r2, hopefully the biggest
superset of L0 parts.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Committed to binutils back in 2012, so even though it has no real impact, it at
least does the right thing for future compilers to make better decisions.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Fix regresion from 5d4437fe43aa68a28611e9a0aecc712833230304 where
somehow not all occurrences were replaced. I could swear it all
compiled when I was working on it :(
Reported-by: Trevor Woerner <trevor.woerner@linaro.org>
Latest versions of all reference manuals refer to the address as SPIx_BASE, and
simply name some of the individual registers as SPI_I2SXXXX. Likewise, the
interrupts are simply SPIx, not SPIx/I2Sx. Rather than hacking more duplicates
into the F0 and L0 parts where this was turning up, remove the pointless _I2S_
from SPI2/SPI3 and make it all consistent
Compile tested only, with the examples collection.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Fixes#331Fixes#347
All methods in this file are in either
* common/gpio_common_all.c
* common/gpio_common_f0234.c
Those other files have better doxygen commentary, this file should never
have been added.
The CCxP/CCxNP bits are actually separated by a reserved bit, so the
correct mask is 0xa, (0b1010) not 0x6 (0b0110)
Reported by PyroDevil on the mailinglist
