Final chunk of register definitions to be pulled up.
Now the "target" files are _only_ defining the list of u(s)arts
available, and any _specific_ functions for that target.
Just small pieces at a time to make it easy to see what's happening.
Taking definitions currently implemented in both f0/f3 headers and
making combined, documented versions in the -v2 header.
Use the usart-common base plus the usart-v2 code, instead of private
implementations. Less code, more common apis across targets.
Of note is the trick to make F0 look like it has an APB2 bus. It's the
only stm32 that doesn't have a documented APB2 bus, but still has
peripherals enabled via an "APB2" register, and they match how other
targets have an APB2. Simply make APB2 an alias of APB1, as it's only
used for clock speed detection.
Instead of declaring that _every_ device has USART1,2,3 and UART4,5, let
the targets themselves define what periphs they do, along with their
USARTx_BASE defines, and let the common headers just have the common
abstractions.
Similar to how we have abstract defines for the stop bits, parity and
flow control common mode namees, provide abstract flag names for the
"standard" flags. This allows us to start using common API code for v1
and v2 uarts
For stm32f3, drop the "compatibility" defines that simply pollute the
namespace, making it confusingly appear as if f3 has both SR and ISR
registers.
Only pulling out the _common_ stuff. This is a single step in a long
process of eliminating all the duplication and "same, but different"
implementations that are stalling adding nice clean easy support for
l0/f7/l4.
This _ignores_ all currently conflict register definitions, even if they
"do the same thing" it just pulls up the common stuff. A subsequent
commit can look at resolving the implementatations to a single version.
Added the CAN1 compatibility aliases as has been done for adc and dac to
make code reuse easier. Only for the magic enums, the raw bit
definitions remain as per the ref mans
Originally suggested as https://github.com/libopencm3/libopencm3/pull/802
the RCC_TIM17 and RCC_TIM18 macros used in the "new" style were ok, just
the old style raw bit definitions.
Reported-by: Karl Hammar <karl@aspodata.se>
rcc_osc_bypass_enable and rcc_osc_bypass_disable have been copy/pasted
around for the last time! There's a compile bit to check for L0/L1, but
otherwise this is just code duplication for no gain.
Originally suggested in https://github.com/libopencm3/libopencm3/pull/399
At least provide macros for each family that allows easy masking of the
full set of reset reason flags. Trying to provide a function that
provides these in random upper bits seems unclear at best.
Reserved bits are marked explicitly in the comments. ASCR defines
are changed to be consistent with the reference manual. HYSCR,
ASMR, CMR and CICR register defines are rewritten to be more
concise and readable.
For both v1 and v2, provide routines to help do arbitrary length
write/read transfers.
Tested with multiple byte writes and reads, for both 100khz and 400khz,
with repeated starts and stop/starts. However, only tested (presently)
with a single i2c target device, a Sensiron SHT21 sensor. Extended
testing against eeproms and alternative devices would be useful
