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Author SHA1 Message Date
Guillaume Revaillot
b9f183bf1e stm32g0: add dma. 
same same, bit for bit, except not ;) - Channel request mapping now
depends on a new DMAMUX peripheral, and there's no default preset.
So, before enabling dma channel after its configuration, request
must be configured by :

dmamux_set_dma_channel_request(DMAMUX1, DMA_CHANNELx, request_number_from_datasheet);
 2019-11-08 13:47:41 +01:00
Karl Palsson
7a27397b9e stm32: rtcv2: don't shift the "month tens" bit 
None of the other masks are shifted, don't shift this field either.

Fixes: https://github.com/libopencm3/libopencm3/issues/1123
 2019-11-06 19:45:20 +00:00
Karl Palsson
6d9139934c devices.data: add some more l0 parts 2019-10-22 10:35:04 +00:00
Karl Palsson
88b32e3ac0 devices.data: stm32f4: add all missing parts 2019-10-22 10:23:18 +00:00
Eivind Alexander Bergem
af0509826d devices.data: Added stm32f410 2019-10-22 09:04:53 +02:00
Karl Palsson
2b54119b78 cm3: scs: drop all duplicate information 
Keeps the best version of the documentation.

Fixes: https://github.com/libopencm3/libopencm3/pull/269
 2019-10-18 22:38:16 +00:00
Karl Palsson
833da4b672 cm3: extract SCB SHPR to the SCB world it belongs to 
Pull out the duplicate into the right file, keeping the newly fixed
version.
 2019-10-18 22:33:23 +00:00
Karl Palsson
3ebd71b464 cm3: extract Coresight LSR/LAR definitions 
Use a single point of definition for the offset, and add it where it was
missing.
 2019-10-18 22:29:13 +00:00
Matt Anderson
d8579dde95 CortexM0: IPR and SHPR are only word addressable 
For ARMv6M, the IPR and SHPR registers are accessible only when
adddressed with a 32bit word read or write.

Currently in libopencm3 all NVIC interrupt priority register accesses
are made using an 8bit read or write, which results in the hardware
ignoring the write or always returning 0 on read.

Address this by introducing NVIC_IPR32() and SCS_SHPR32() macro and
conditional implementation of nvic_set_priority when building for
cortex-m0.

See ARMv6M developer documentation:
IPR: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/Cihgjeed.html
SHPR: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/CIAGECDD.html
 2019-10-17 21:26:13 +00:00
Karl Palsson
baa2f13592 swm050: doc: tweak peripheral apis groupings 
Makes it more consistent with the other families.
 2019-10-17 11:41:55 +00:00
Caleb Szalacinski
3c4ee6f4c0 SWM050: Finishes GPIO, IAP flash, sysclock, sleep/stop, and the sysctl memory map. 
Updates the main memory map and the makefile.
Adds the SWM050 to devices.data, so that a linker script can be automatically generated.

Reviewed-by: Karl Palsson <karlp@tweak.net.au>
 2019-10-17 11:41:33 +00:00
Bryan PEREIRA
1fbfdecb17 stm32f3: Add SPI4 BASE 2019-10-16 14:41:00 +00:00
Nicholas Rossomando
77d96a3430 stm32l0: crc: enable common code 2019-10-12 14:11:39 +00:00
Karl Palsson
b5d66ee63f devices.data: add all missing stm32f3 parts 
Filled missing variants, added missing families, corrected one or two
mistakes in ccm availability

Fixes: https://github.com/libopencm3/libopencm3/pull/1109
 2019-10-03 11:37:47 +00:00
Karl Palsson
66e6a2092e doc: stm32f1: gpio: remove redundant doxygen types 
Fixes https://github.com/libopencm3/libopencm3/issues/1108
 2019-09-30 10:28:21 +00:00
Jonathan Halmen
ec2d96433f stm32f4: rcc: add plli2s config function 2019-09-27 13:55:56 +00:00
Jonathan Halmen
203d0ca295 stm32f4: rcc: remove unnecessary pllsai functions 
existing standard functions for these are
 * rcc_osc_on(RCC_PLLSAI);
 * rcc_is_osc_ready(RCC_PLLSAI);
 2019-09-27 13:43:06 +00:00
Matthew Lai
5fbe5c8c47 devices.data: Added STM32F7 value line devices with 64K flash 2019-09-23 22:45:36 +00:00
Karl Palsson
b0c3de8d85 devices.data: add missing stm32f301 parts 
Fixes: https://github.com/libopencm3/libopencm3/issues/1098
 2019-09-03 22:23:26 +00:00
Guillaume Revaillot
8a1cfa8ceb stm32g0: use proper register for gpio peripheral clock sleep enable. 
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
 2019-08-28 20:54:35 +00:00
Guillaume Revaillot
998e647dde stm32g0: memorymap: get rid of apb1/apb2 reference, device only has one apb. 
I apparently based memorymap.h on previously written header without noticing
that g0 has only one apb despite a big hole in the memory space and addresses
matching usual apb1/apb2 split..
 2019-08-28 12:03:55 +02:00
Guillaume Revaillot
1928e6eb3c doc: typo 2019-08-28 01:41:14 +00:00
Guillaume Revaillot
562dca7358 stm32f4: doc: f4 are cortex m4f based 2019-08-28 01:41:14 +00:00
Guillaume Revaillot
ec597796d7 stm32g0: fix bad typos in memorymap, impacting tim1 and tim15-17. 2019-08-27 16:24:42 +02:00
Karl Palsson
7ff54cb7f0 devices.data: add more stm32l1 parts 
Fixes some eeprom sizes, and adds all the -a and -x suffix parts.
Note that the explicit endings must be listed _before_ the base parts,
otherwise the matcher will find the wild card first.

Signed-off-by: Karl Palsson <karlp@etactica.com>
 2019-08-22 10:01:11 +00:00
Guillaume Revaillot
3eff201a4b doc: stm32: adc: upgrade common_v2 documentation 
add register grouping, fixup comment have them pickedup by doxygen, align style and masks.
 2019-07-06 15:38:49 +00:00
Guillaume Revaillot
2035d84e55 stm32: lptim: add base support 
Add basically what's needed to have some minimal but usefull subset of
function for a timer: irqs, compare, period, out polarity, enable/disable
and start.
 2019-07-05 11:43:11 +02:00
Guillaume Revaillot
f99e711873 stm32g0: lptim: add additional cr bits and cfgr2 reg. 2019-07-05 11:43:11 +02:00
Guillaume Revaillot
811aebf096 stm32: lptimer: enable lptimer.h usage on f4,f7,l4 and g0 chips. 2019-07-05 10:48:55 +02:00
Guillaume Revaillot
2975c3151a stm32: extract l0 lptimer stuff from timer.h to common lptimer.h 
lptimer peripheral is present on f4,f7,l0,l4,g0,g4 and prob others. Extract
content from stm32l0 timer.h and make it usable by other chips.
 2019-07-05 10:48:26 +02:00
Guillaume Revaillot
689e326f5f stm32f4: lptim1 sits at 0x40002400 on stm32f410, update memorymap 2019-07-02 18:27:43 +02:00
Karl Palsson
6894965408 gadget0: f429: update to newest rcc api 2019-07-02 09:34:28 +00:00
Karl Palsson
43b6f333d2 gadget0: f4: update to newest rcc api 2019-06-28 21:45:14 +00:00
Karl Palsson
1519b435ca gadget0: f4: PA9 is not an AF. 
It has never been an AF, it's always been an error to set this pin to
AF.
 2019-06-28 21:45:14 +00:00
Karl Palsson
7c24f0f837 gadget0: allow parallel submake 
allows "make -j10" work properly
 2019-06-28 21:45:14 +00:00
Karl Palsson
8b4d952629 doc: stm32f3: adc: add missing parameters 
Minor, link the adc peripheral parameter in a couple of places
 2019-06-27 14:53:09 +00:00
Karl Palsson
9b3c813399 doc: lm3s: escape email address to avoid xml interp 2019-06-27 14:53:09 +00:00
Karl Palsson
38d88c6113 doc: stm32f0: rcc: add missing groups for pll factors and sources 2019-06-27 14:53:09 +00:00
Karl Palsson
06ee2009e8 doc: gd32f1x0: merge flash and rcc into periperhal apis 
Instead of having some in peripheral_apis and some under the target
itself
 2019-06-27 14:53:09 +00:00
Karl Palsson
8744df10a6 doc: gd32: make groups match what's used. 
Fixes the missing top level groupings here.
 2019-06-25 21:15:35 +00:00
Karl Palsson
0cd06bcc97 doc: gd32/f1x0: fix missing tags, drop wrong tags 
Drop incorrect/redundant type information from doxygen parameters
Adds groupings that are referred to.
 2019-06-25 21:15:35 +00:00
Karl Palsson
1964fd72f2 doc: stm32f3: adc: register base addresses had landed outside a group 2019-06-25 21:15:35 +00:00
Karl Palsson
668cfb2967 doc: cm3: scb: add basic documentation 
Adds a summary page, and now we have the existing functions documented.
 2019-06-25 21:15:31 +00:00
Karl Palsson
e5b5ba0f9c doc: cm3: dwt: include existing documentation 2019-06-25 21:15:24 +00:00
Karl Palsson
1b10a0871c doc: cm3: mpu: fix typo 2019-06-25 21:15:19 +00:00
Karl Palsson
60991ac306 doc: cm3: nvic: convert existing docs to doxygen 
Make it visible
 2019-06-25 21:15:19 +00:00
Karl Palsson
69ce9f876f doc: core cm3: standard titles 
easier on the eyes reading the list of docs
 2019-06-25 21:15:19 +00:00
Karl Palsson
f63145db07 doc: stm32f7: rcc: add missing top level groups 2019-06-25 21:15:19 +00:00
Karl Palsson
1f359e0cb8 doc: efm32: tag USB files for doxygen generation 2019-06-25 21:15:19 +00:00
Karl Palsson
2d1277e1fa doc: efm32: uart/usart provide common doxygen 
Fix some direct includes, tag properly, include a stub file to pull in
shared header documentation and re-arrange some existing documentation
to make it present nicely.
 2019-06-25 21:15:19 +00:00