Tested with a Lora radio application that used three GPIO lines to send
different interrupts from the radio module to the L052. Tested with a
Jeenode Zero Rev1
While the NOLOAD variant sometimes worked with some toolchains, the
version in the generator scripts could never work, as neither the
startup code, nor gdb know how to load those sections properly.
Originally added in: eb18cc19cb392a69f8675c42776c644d1003ed89
The original scripts allowed you to place variables in eeprom space for
reading only. However, the last toolchain that generated working code
with this linker script was the gcc-arm-none-eabi-4_9-2014q4 release.
Subsequent releases treat the directives differently, and can lose track
of where variables are. One known symptom is constants getting bad
addresses, so for instance, "printf("asdfad")" will end up passing the
wrong address of the string constant into the eventual _write() call.
This commit removes the problematic directives until a more fully
correct system can be found that more properly follows the linker
script rules.
Attempts to helpfully unlock PECR when required in unlock_progmem and
unlock_option_bytes actually cause a bus error due to repeated unlocks,
as per ref manual and tedious experience. The better tested eeprom helper
routines unlock/lock in chunks, but that's not applicable for flash
writing.
Fixes: cf5fb002f6016242fb23b81fcbe98ee022bb84e9
The previous implementation of copy_from_pm assumed the destination buffer
was aligned on a 16-bit boundary. On M0/M0+ cores (stm32F0*, stm32L0*)
this causes a hard fault.
This implementation is from Kuldeep Dhaka's tree; it does a 16-bit copy
only if the destination buffer is aligned, otherwise a bytewise copy.
Fixes GH issues #401, #461
The f107 ethernet peripheral is the same as in f4, and was pulled out
into lib/ethernet/mac_stm32fxx7.c in 52758bb8fdf065d46ef1ea21cc383e2dc74ee19b
This drops the duplicate code.
Fixes Github issue #694
The TSVREFE bit is defined to only be present on ADC1, so drop the
pointless adc argument. This has the added benefit of making the
API consistent with all other STM32 adc parts.
Use same names as adv-v2 peripheral uses. F1 is the only v1 peripheral
adc that has calibration modes at all.
Old:
adc_calibration(ADC1); // blocking call
New (blocking):
adc_calibrate(ADC1);
New (asynch):
adc_calibrate_async(ADC1);
// do stuff
adc_is_calibrating(ADC1); // false when calibration finished
Old routines are preserved but marked deprecated for now.
Extract the calibration code from the f0, and share it with the other
adc-v2 peripheral users (f0,l0,f3,l4)
Uses the same naming set of is/async naming conventions requested by the
RTOS guys instead of having blocking only calls.
Old code:
adc_calibrate_start(ADC);
adc_calibrate_wait_finish(ADC);
New code (blocking):
adc_calibrate(ADC);
New code (asynch):
adc_calibrate_async(ADC);
// do stuff
adc_is_calibrating(ADC); // will be false when it's finished.
Old code for f0 is still available, but marked deprecated.
Fixes: 57c2b00a69f97205313e1c7ab8116ee1893b231e
There was an issue with the pllp value calculation where the masking was done
in the wrong place. The pllp value was always equivalent to 2 (the bits were
always set to 0b00) which could result in an undesired system clock frequency.
When changing the system clock, you must take care to not exceed the
legal ranges based on voltage and flash wait states.
Existing code made it possible to provide a valid clock structure, that
would run out of bounds temporarily. Some boards would crash with
various Usage faults / Bus errors due to this.
These functions have existed since the initial commit, fallout from
copying an existing file and then trying to implement functions as
needed. F3 ADC doesn't have corresponding functions for some of these,
and this dead code should never have landed. Dropping it for clarity,
and also to stop confusing doxygen.
Start providing async routines for all blocking routines, to make it
easier to use libopencm3 in some RTOS environments. This is not in
anyway intended to be complete, this just covers a single blocking
routine, rcc_wait_for_osc_ready. Documentation added to the top level,
and provided for all stm32 families.
This is common code for f0234, keep renaming files as has become standard, even
if it's a suboptimal solution. This doesn't rename the header which was not
renamed for f3.
Reported-by: https://github.com/gtoonstra
Original implementation only checked whether the user had _selected_ the
clock, not whether it had actually switched to the clock or not. For
almost all cases, this made this function either a no-op, if you _had_
selected the clock, or a blocking loop if you hadn't selected it ahead
of time.
Fixes github issue #687
This was inspired by an Arch Linux provided ARM GCC 5.3.0 bug:
It gave an
"internal compiler error: in expand_expr_addr_expr_1, at expr.c:7736"
with the array version of the desig_get_unique_id.
While I was at it, fixed:
- a potential alignment issue with casting uint8_t* buf to uint32_t*
- a funny static in the string definition that does nothing (given const)
This reverts commit aa5e108553ace3079c6087dec796b9e58fe45fa4.
This commit was not meant to land yet, it should have gone for review, and
doesn't yet include all the parts it should touch.
replace bulky hardcoded wait for set and wait for clear with a single asynch
routine. Leave the blocking routines in for compatibility at this point.
NOUP: should be added to other rcc.c files too.
Helpful if you don't like seeing:
(gdb) vecstate
HardFault: forced due to escalated or disabled configurable fault (see below)
UsageFault due to access to disabled/absent coprocessor
L4 and F3 actually have the same bits to write in the same order, but F3 hides
the name of the deep power down bit. Keep the like that for now, but there's a
standard API for enabling and disabling the regulator.
