Extension of code for STM32F1 to allow for dual bank series XL.
Small changes to documentation for F2, F4 and L1 to add a parameter reference.
Tested with STM32F103RBT6
(note: tests show that the PG bit must be cleared after programming, otherwise
a subsequent erase attempt fails. This has been added to flash_program_half_word
for F0 and F1 only. A fix for the other families is not included in this PR.)
This unifies stm32f1, l1, and f4 convenience functions for adc. The code
should be useable for f2 and f37x as well, but that needs hardware for testing,
and there was no existing implementation. This is the reason for the
"adc_common_v1.c" name, as trying to put all the different families into the
common file name has become too cumbersome.
All of the deprecated routines have been dropped, they've been marked
deprecated for a very long time now, and porting them seemed unnecessary.
This has been tested on f1, l1 and f4 discovery boards, and is based on some
existing l1/f1 unification code from
https://github.com/karlp/libopencm3/tree/rme_l1_master
So that the navigation pane works correctly in browsers.
Some additional doc fixes put in where found (but many more still to go).
Added some dummy .c and .h files to bring the associated docs into line.
makefile changed to allow 'make html' as well as 'make doc' (the latter only does html anyway).
The common code wasn't being included in L1 builds, even though the headers now
included the correct definitions.
This combines the two f0 and f3 spi files, which previously differed only in
the number of spi peripherals defined.
Files were renamed to the full "l1f124" style, not because I like it, but
because it's the convention we have, so it's best to apply it rigourously.
Tested on L1 and F100 boards, compile tested only for others, but the examples
repository all compiles too. (Though the lack of SPI examples for all
platforms was how this broke in the first place)
We don't support f0 yet so let's not fool anyone. We may rename those
files back again if when we cross check that it is actually true this
file supports f0.
- Several functions added (that only work on the f3)
- The data register now has a 8bit access counter part
that is necessary for 8bit transmissions, together with
the access functions.
- The init master functions doesn't work for the f3.
- Makefiles of other stm32s updated accordingly.
- f3/rcc.c updated to some definition changes.
- f3/flash.c removed in order to use flash_common_f234.c to comply with new organization.
- Makefiles now include building f3 src directory.
- Gpio support added. gpio_common_f24 changed to support also f3.
- f3 still not compiling, but f2 compile not broken (probably also f4).
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.
We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
only contain one statement. Otherwise it is easy to introduce an
error.
Checkpatch needs to be adapted to reflect those changes.
Added hash processor register definitions and main functions. Hash
processor is supported in stm32f21, stm32f41 and stm32f43 and can be
used to calculate Md5 and Sha1.
Change flash_erase_sector (f2/f4) to take numerical sector argument.
As opposed to using one of the defines in the header, this is more convenient when programatically deciding which sectors to erase.
f1/timer.
Added timer_ic_set_polarity to timer_common_f24 with
the enum tim_ic_pol now including trigger on both edges.
Changed timer_slave_set_polarity to use enum tim_et_pol
rather than tim_ic_pol.
In response to suggestion of stinkydiver73 on 24 March that
timers in all families have an option for triggers on both
edges, except F1.
