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First coarse run to fix coding style in locm3.

Browse Source 
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.

We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
  only contain one statement. Otherwise it is easy to introduce an
  error.

Checkpatch needs to be adapted to reflect those changes.
This commit is contained in:
Piotr Esden-Tempski 2013-06-12 17:44:07 -07:00
parent 48e0f3326b
commit 7df63fcae0
147 changed files with 3323 additions and 2565 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Makefile
View File

@ -21,7 +21,7 @@ PREFIX ?= arm-none-eabi
#PREFIX ?= arm-elf
STYLECHECK := scripts/checkpatch.pl
STYLECHECKFLAGS := --no-tree -f
STYLECHECKFLAGS := --no-tree -f --terse --mailback
ifeq ($(DETECT_TOOLCHAIN),)
DESTDIR ?= /usr/local
@ -102,7 +102,7 @@ clean: cleanheaders
stylecheck:
$(Q)for i in `find . -name '*.[ch]'` ; do \
if ! grep -q "* It was generated by the irq2nvic_h script." $$i ; then \
$(STYLECHECK) $(STYLECHECKFLAGS) $$i || exit $?; \
$(STYLECHECK) $(STYLECHECKFLAGS) $$i; \
fi ; \
done

31
include/libopencm3/cm3/assert.h
View File

@ -49,25 +49,26 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/cm3/common.h>
#define CM3_LIKELY(expr) (__builtin_expect (!!(expr), 1))
#define CM3_LIKELY(expr) (__builtin_expect(!!(expr), 1))
#ifdef NDEBUG
# define cm3_assert(expr) do { (void)0; } while(0)
# define cm3_assert_not_reached() while(1)
# define cm3_assert(expr) (void)0
# define cm3_assert_not_reached() do { } while (1)
#else
# ifdef CM3_ASSERT_VERBOSE
# define cm3_assert(expr) do { \
if(CM3_LIKELY(expr)) { (void)0; } else { \
if (CM3_LIKELY(expr)) { \
(void)0; \
} else { \
cm3_assert_failed_verbose( \
__FILE__, __LINE__, \
__func__, #expr); \
} \
} while(0)
# define cm3_assert_not_reached() do { \
} while (0)
# define cm3_assert_not_reached() \
cm3_assert_failed_verbose( \
__FILE__, __LINE__, \
__func__, 0); \
} while(0)
__func__, 0)
# else
/** @brief Check if assertion is true.
*
@ -82,10 +83,12 @@ LGPL License Terms @ref lgpl_license
*
* @param expr expression to check */
# define cm3_assert(expr) do { \
if(CM3_LIKELY(expr)) { (void)0; } else { \
if (CM3_LIKELY(expr)) { \
(void)0; \
} else { \
cm3_assert_failed(); \
} \
} while(0)
} while (0)
/** @brief Check if unreachable code is reached.
*
* If NDEBUG macro is defined, this macro generates code for an infinite loop.
@ -95,9 +98,7 @@ LGPL License Terms @ref lgpl_license
* The purpose of this macro is to aid in debugging libopencm3 and
* applications using it. It can be used for example to stop execution if an
* unreachable portion of code is reached. */
# define cm3_assert_not_reached() do { \
cm3_assert_failed(); \
} while(0)
# define cm3_assert_not_reached() cm3_assert_failed()
# endif
#endif
@ -111,7 +112,7 @@ BEGIN_DECLS
* implementation. Usually, a custom implementation of this function should
* report an error in some way (print a message to a debug console, display,
* LED, ...) and halt execution or reboot the device. */
void cm3_assert_failed(void) __attribute__ ((__noreturn__));
void cm3_assert_failed(void) __attribute__((__noreturn__));
/** @brief Called on a failed assertion with verbose messages enabled.
*
@ -127,7 +128,7 @@ void cm3_assert_failed(void) __attribute__ ((__noreturn__));
* @param func Name of the function where the failed assertion occurred
* @param assert_expr Expression that evaluated to false (can be NULL) */
void cm3_assert_failed_verbose(const char *file, int line, const char *func,
const char *assert_expr) __attribute__ ((__noreturn__));
const char *assert_expr) __attribute__((__noreturn__));
END_DECLS

7
include/libopencm3/cm3/common.h
View File

@ -46,9 +46,9 @@ typedef uint64_t u64;
#ifdef __GNUC__
# if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ > 4)
# define LIBOPENCM3_DEPRECATED(x) __attribute__ ((deprecated (x)))
# define LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))
# else
# define LIBOPENCM3_DEPRECATED(x) __attribute__ ((deprecated))
# define LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated))
# endif
#else
# define LIBOPENCM3_DEPRECATED(x)
@ -95,4 +95,7 @@ typedef uint64_t u64;
#define BIT30 (1<<30)
#define BIT31 (1<<31)
#define __packed __attribute__((packed))
#define __aligned(x) __attribute__((aligned(x)))
#endif

22
include/libopencm3/cm3/nvic.h
View File

@ -44,37 +44,43 @@ LGPL License Terms @ref lgpl_license
/* ISER: Interrupt Set Enable Registers */
/* Note: 8 32bit Registers */
#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + \
(iser_id * 4))
/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
/* ICER: Interrupt Clear Enable Registers */
/* Note: 8 32bit Registers */
#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4))
#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + \
(icer_id * 4))
/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
/* ISPR: Interrupt Set Pending Registers */
/* Note: 8 32bit Registers */
#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4))
#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + \
(ispr_id * 4))
/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
/* ICPR: Interrupt Clear Pending Registers */
/* Note: 8 32bit Registers */
#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4))
#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + \
(icpr_id * 4))
/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
/* IABR: Interrupt Active Bit Register */
/* Note: 8 32bit Registers */
#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4))
#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + \
(iabr_id * 4))
/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
/* IPR: Interrupt Priority Registers */
/* Note: 240 8bit Registers */
#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id)
#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + \
ipr_id)
/* STIR: Software Trigger Interrupt Register */
#define NVIC_STIR MMIO32(STIR_BASE)
@ -104,12 +110,12 @@ IRQ numbers -3 and -6 to -9 are reserved
* specific header file in the corresponding subfolder.
*/
#define WEAK __attribute__((weak))
#include <libopencm3/dispatch/nvic.h>
/* --- NVIC functions ------------------------------------------------------ */
#define WEAK __attribute__ ((weak))
BEGIN_DECLS
void nvic_enable_irq(u8 irqn);

2
include/libopencm3/cm3/scb.h
View File

@ -374,7 +374,7 @@ struct scb_exception_stack_frame {
u32 lr;
u32 pc;
u32 xpsr;
} __attribute__((packed));
} __packed;
#define SCB_GET_EXCEPTION_STACK_FRAME(f) \
do { \

151
include/libopencm3/cm3/scs.h
View File

@ -24,12 +24,14 @@
/*
* All the definition hereafter are generic for CortexMx ARMv7-M
* See ARM document "ARMv7-M Architecture Reference Manual" for more details.
* See also ARM document "ARM Compiler toolchain Developing Software for ARM Processors" for details on System Timer/SysTick.
* See also ARM document "ARM Compiler toolchain Developing Software for ARM
* Processors" for details on System Timer/SysTick.
*/
/*
* The System Control Space (SCS) is a memory-mapped 4KB address space that provides 32-bit registers for
* configuration, status reporting and control. The SCS registers divide into the following groups:
* The System Control Space (SCS) is a memory-mapped 4KB address space that
* provides 32-bit registers for configuration, status reporting and control.
* The SCS registers divide into the following groups:
* - system control and identification
* - the CPUID processor identification space
* - system configuration and status
@ -48,12 +50,14 @@
* Debug Halting Control and Status Register (DHCSR).
*
* Purpose Controls halting debug.
* Usage constraints: The effect of modifying the C_STEP or C_MASKINTS bit when the system
* is running with halting debug enabled is UNPREDICTABLE.
* Halting debug is enabled when C_DEBUGEN is set to 1. The system is running when S_HALT is set to 0.
* - When C_DEBUGEN is set to 0, the processor ignores the values of all other bits in this register.
* - For more information about the use of DHCSR see Debug stepping on
* page C1-824.
* Usage constraints: The effect of modifying the C_STEP or C_MASKINTS bit when
* the system is running with halting debug enabled is UNPREDICTABLE.
* Halting debug is enabled when C_DEBUGEN is set to 1. The system is running
* when S_HALT is set to 0.
* - When C_DEBUGEN is set to 0, the processor ignores the values of all other
* bits in this register.
* - For more information about the use of DHCSR see Debug stepping on page
* C1-824.
* Configurations Always implemented.
*/
/* SCS_DHCSR register */
@ -61,10 +65,10 @@
/*
* Debug Core Register Selector Register (DCRSR).
*
* Purpose With the DCRDR, the DCRSR provides debug access to the ARM core registers,
* special-purpose registers, and Floating-point extension registers. A write to DCRSR
* specifies the register to transfer, whether the transfer is a read or a write, and starts
* the transfer.
* Purpose With the DCRDR, the DCRSR provides debug access to the ARM core
* registers, special-purpose registers, and Floating-point extension
* registers. A write to DCRSR specifies the register to transfer, whether the
* transfer is a read or a write, and starts the transfer.
* Usage constraints: Only accessible in Debug state.
* Configurations Always implemented.
*
@ -74,14 +78,15 @@
/*
* Debug Core Register Data Register (DCRDR)
*
* Purpose With the DCRSR, see Debug Core Register Selector Register,
* the DCRDR provides debug access to the ARM core registers,
* special-purpose registers, and Floating-point extension registers. The
* DCRDR is the data register for these accesses.
* - Used on its own, the DCRDR provides a message passing resource between
* an external debugger and a debug agent running on the processor.
* Purpose With the DCRSR, see Debug Core Register Selector Register, the DCRDR
* provides debug access to the ARM core registers, special-purpose registers,
* and Floating-point extension registers. The DCRDR is the data register for
* these accesses.
* - Used on its own, the DCRDR provides a message passing resource between an
* external debugger and a debug agent running on the processor.
* Note:
* The architecture does not define any handshaking mechanism for this use of DCRDR.
* The architecture does not define any handshaking mechanism for this use of
* DCRDR.
* Usage constraints: See Use of DCRSR and DCRDR for constraints that apply to
* particular transfers using the DCRSR and DCRDR.
* Configurations Always implemented.
@ -92,7 +97,8 @@
/*
* Debug Exception and Monitor Control Register (DEMCR).
*
* Purpose Manages vector catch behavior and DebugMonitor handling when debugging.
* Purpose Manages vector catch behavior and DebugMonitor handling when
* debugging.
* Usage constraints:
* - Bits [23:16] provide DebugMonitor exception control.
* - Bits [15:0] provide Debug state, halting debug, control.
@ -143,20 +149,22 @@
/*
* System Control Space (SCS) => System timer register support in the SCS.
* To configure SysTick, load the interval required between SysTick events to the SysTick Reload
* Value register. The timer interrupt, or COUNTFLAG bit in the SysTick Control and Status
* register, is activated on the transition from 1 to 0, therefore it activates every n+1 clock ticks.
* If you require a period of 100, write 99 to the SysTick Reload Value register. The SysTick Reload
* Value register supports values between 0x1 and 0x00FFFFFF.
* To configure SysTick, load the interval required between SysTick events to
* the SysTick Reload Value register. The timer interrupt, or COUNTFLAG bit in
* the SysTick Control and Status register, is activated on the transition from
* 1 to 0, therefore it activates every n+1 clock ticks. If you require a
* period of 100, write 99 to the SysTick Reload Value register. The SysTick
* Reload Value register supports values between 0x1 and 0x00FFFFFF.
*
* If you want to use SysTick to generate an event at a timed interval, for example 1ms, you can
* use the SysTick Calibration Value Register to scale your value for the Reload register. The
* SysTick Calibration Value Register is a read-only register that contains the number of pulses for
* a period of 10ms, in the TENMS field, bits[23:0].
* If you want to use SysTick to generate an event at a timed interval, for
* example 1ms, you can use the SysTick Calibration Value Register to scale
* your value for the Reload register. The SysTick Calibration Value Register
* is a read-only register that contains the number of pulses for a period of
* 10ms, in the TENMS field, bits[23:0].
*
* This register also has a SKEW bit. Bit[30] == 1 indicates that the calibration for 10ms in the
* TENMS section is not exactly 10ms due to clock frequency. Bit[31] == 1 indicates that the
* reference clock is not provided.
* This register also has a SKEW bit. Bit[30] == 1 indicates that the
* calibration for 10ms in the TENMS section is not exactly 10ms due to clock
* frequency. Bit[31] == 1 indicates that the reference clock is not provided.
*/
/*
* SysTick Control and Status Register (CSR).
@ -199,23 +207,27 @@
/* SysTick uses the processor clock. */
#define SCS_SYST_CSR_CLKSOURCE (BIT2)
/*
* Indicates whether the counter has counted to 0 since the last read of this register:
* Indicates whether the counter has counted to 0 since the last read of this
* register:
* 0 = Timer has not counted to 0
* 1 = Timer has counted to 0.
*/
#define SCS_SYST_CSR_COUNTFLAG (BIT16)
/* --- CM_SCS_SYST_RVR values ----------------------------------------------- */
/* Bit 0 to 23 => RELOAD The value to load into the SYST_CVR when the counter reaches 0. */
/* --- CM_SCS_SYST_RVR values ---------------------------------------------- */
/* Bit 0 to 23 => RELOAD The value to load into the SYST_CVR when the counter
* reaches 0.
*/
/* Bit 24 to 31 are Reserved */
/* --- CM_SCS_SYST_CVR values ----------------------------------------------- */
/* --- CM_SCS_SYST_CVR values ---------------------------------------------- */
/* Bit0 to 31 => Reads or clears the current counter value. */
/* --- CM_SCS_SYST_CALIB values ----------------------------------------------- */
/* --- CM_SCS_SYST_CALIB values -------------------------------------------- */
/*
* Bit0 to 23 => TENMS Optionally, holds a reload value to be used for 10ms (100Hz) timing, subject to system clock
* skew errors. If this field is zero, the calibration value is not known.
* Bit0 to 23 => TENMS Optionally, holds a reload value to be used for 10ms
* (100Hz) timing, subject to system clock skew errors. If this field is zero,
* the calibration value is not known.
*/
#define SCS_SYST_SYST_CALIB_TENMS_MASK (BIT24-1)
@ -226,44 +238,54 @@
*/
#define SCS_SYST_SYST_CALIB_VALUE_INEXACT (BIT30)
/*
* Bit31 => NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock is implemented:
* Bit31 => NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock
* is implemented:
* 0 = The reference clock is implemented.
* 1 = The reference clock is not implemented.
* When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to 1 and cannot
* be cleared to 0.
* When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to
* 1 and cannot be cleared to 0.
*/
#define SCS_SYST_SYST_CALIB_REF_NOT_IMPLEMENTED (BIT31)
/*
* System Control Space (SCS) => Data Watchpoint and Trace (DWT).
* See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0403c/index.html (ARMv7-M Architecture Reference Manual)
* The DWT is an optional debug unit that provides watchpoints, data tracing, and system profiling
* for the processor.
* See http://goo.gl/mZm30 (ARMv7-M Architecture Reference Manual)
* The DWT is an optional debug unit that provides watchpoints, data tracing,
* and system profiling for the processor.
*/
/*
* DWT Control register
* Purpose Provides configuration and status information for the DWT block, and used to control features of the block
* Purpose Provides configuration and status information for the DWT block, and
* used to control features of the block
* Usage constraints: There are no usage constraints.
* Configurations Always implemented.
*/
#define SCS_DWT_CTRL MMIO32(DWT_BASE + 0x00)
/*
* DWT_CYCCNT register
* Cycle Count Register (Shows or sets the value of the processor cycle counter, CYCCNT)
* When enabled, CYCCNT increments on each processor clock cycle. On overflow, CYCCNT wraps to zero.
* Cycle Count Register (Shows or sets the value of the processor cycle
* counter, CYCCNT)
* When enabled, CYCCNT increments on each processor clock cycle. On overflow,
* CYCCNT wraps to zero.
*
* Purpose Shows or sets the value of the processor cycle counter, CYCCNT.
* Usage constraints: The DWT unit suspends CYCCNT counting when the processor is in Debug state.
* Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control register, DWT_CTRL.
* When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this register is UNK/SBZP.
* Usage constraints: The DWT unit suspends CYCCNT counting when the processor
* is in Debug state.
* Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control
* register, DWT_CTRL.
* When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this
* register is UNK/SBZP.
*/
#define SCS_DWT_CYCCNT MMIO32(DWT_BASE + 0x04)
/* DWT_CPICNT register
* Purpose Counts additional cycles required to execute multi-cycle instructions and instruction fetch stalls.
* Usage constraints: The counter initializes to 0 when software enables its counter overflow event by
* Purpose Counts additional cycles required to execute multi-cycle
* instructions and instruction fetch stalls.
* Usage constraints: The counter initializes to 0 when software enables its
* counter overflow event by
* setting the DWT_CTRL.CPIEVTENA bit to 1.
* Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control register, DWT_CTRL.
* Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control
* register, DWT_CTRL.
* If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not
* include the profiling counters, this register is UNK/SBZP.
*/
@ -284,7 +306,7 @@
/* DWT_PCSR register */
#define SCS_DWT_PCSR MMIO32(DWT_BASE + 0x18)
/* --- SCS_DWT_CTRL values ----------------------------------------------- */
/* --- SCS_DWT_CTRL values ------------------------------------------------- */
/*
* Enables CYCCNT:
* 0 = Disabled, 1 = Enabled
@ -295,15 +317,20 @@
/* TODO bit definition values for other DWT_XXX register */
/* Macro to be called at startup to enable SCS & Cycle Counter */
#define SCS_DWT_CYCLE_COUNTER_ENABLED() ( (SCS_DEMCR |= SCS_DEMCR_TRCENA)\
(SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA) )
#define SCS_DWT_CYCLE_COUNTER_ENABLED() ((SCS_DEMCR |= SCS_DEMCR_TRCENA)\
(SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA))
#define SCS_SYSTICK_DISABLED() (SCS_SYST_CSR=0)
#define SCS_SYSTICK_DISABLED() (SCS_SYST_CSR = 0)
/* Macro to be called at startup to Enable CortexMx SysTick (but IRQ not enabled) */
#define SCS_SYSTICK_ENABLED() (SCS_SYST_CSR=(SCS_SYST_CSR_ENABLE | SCS_SYST_CSR_CLKSOURCE))
/* Macro to be called at startup to Enable CortexMx SysTick (but IRQ not
* enabled)
*/
#define SCS_SYSTICK_ENABLED() (SCS_SYST_CSR = (SCS_SYST_CSR_ENABLE | \
SCS_SYST_CSR_CLKSOURCE))
/* Macro to be called at startup to Enable CortexMx SysTick and IRQ */
#define SCS_SYSTICK_AND_IRQ_ENABLED() (SCS_SYST_CSR=(SCS_SYST_CSR_ENABLE | SCS_SYST_CSR_CLKSOURCE | SCS_SYST_CSR_TICKINT))
#define SCS_SYSTICK_AND_IRQ_ENABLED() (SCS_SYST_CSR = (SCS_SYST_CSR_ENABLE | \
SCS_SYST_CSR_CLKSOURCE | \
SCS_SYST_CSR_TICKINT))
#endif

8
include/libopencm3/cm3/sync.h
View File

@ -29,8 +29,8 @@
/* --- Exclusive load and store instructions ------------------------------- */
u32 __ldrex(volatile u32* addr);
u32 __strex(u32 val, volatile u32* addr);
u32 __ldrex(volatile u32 *addr);
u32 __strex(u32 val, volatile u32 *addr);
void __dmb(void);
/* --- Convenience functions ----------------------------------------------- */
@ -42,7 +42,7 @@ typedef u32 mutex_t;
#define MUTEX_UNLOCKED 0
#define MUTEX_LOCKED 1
void mutex_lock(mutex_t* m);
void mutex_unlock(mutex_t* m);
void mutex_lock(mutex_t *m);
void mutex_unlock(mutex_t *m);
#endif

2
include/libopencm3/cm3/vector.h
View File

@ -45,7 +45,7 @@
typedef void (*vector_table_entry_t)(void);
typedef struct {
unsigned int *initial_sp_value; /**< The value the stack pointer is set to initially */
unsigned int *initial_sp_value; /**< Initial stack pointer value. */
vector_table_entry_t reset;
vector_table_entry_t nmi;
vector_table_entry_t hard_fault;

3
include/libopencm3/lm3s/gpio.h
View File

@ -6,7 +6,8 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2011 Gareth McMullin <gareth@blacksphere.co.nz>
@author @htmlonly &copy; @endhtmlonly 2011
Gareth McMullin <gareth@blacksphere.co.nz>
@date 10 March 2013

3
include/libopencm3/lm3s/systemcontrol.h
View File

@ -6,7 +6,8 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2011 Gareth McMullin <gareth@blacksphere.co.nz>
@author @htmlonly &copy; @endhtmlonly 2011
Gareth McMullin <gareth@blacksphere.co.nz>
@date 10 March 2013

6
include/libopencm3/lm4f/gpio.h
View File

@ -6,8 +6,10 @@
*
* @version 1.0.0
*
* @author @htmlonly &copy; @endhtmlonly 2011 Gareth McMullin <gareth@blacksphere.co.nz>
* @author @htmlonly &copy; @endhtmlonly 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
* @author @htmlonly &copy; @endhtmlonly 2011
* Gareth McMullin <gareth@blacksphere.co.nz>
* @author @htmlonly &copy; @endhtmlonly 2013
* Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* @date 16 March 2013
*

12
include/libopencm3/lm4f/nvic.h
View File

@ -1,12 +1,14 @@
/** @defgroup nvic_defines Nested Vectored Interrupt Controller
@brief <b>Defined Constants and Types for the LM4F Nested Vectored Interrupt Controller</b>
@brief <b>Defined Constants and Types for the LM4F Nested Vectored Interrupt
Controller</b>
@ingroup LM4Fxx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012
Alexandru Gagniuc <mr.nuke.me@gmail.com>
@date 10 March 2013
@ -40,9 +42,9 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/cm3/nvic.h>
/** @ingroup nvic_defines
* The LM3S interrupt table applies to the LM4F as well.
* Some interrupt vectors marked as reserved in LM3S are used in LM4F, and some
* vectors in LM3S are marked reserved for LM4F. However, the common vectors are
* The LM3S interrupt table applies to the LM4F as well. Some interrupt
* vectors marked as reserved in LM3S are used in LM4F, and some vectors in
* LM3S are marked reserved for LM4F. However, the common vectors are
* identical, and we can safely use the same interrupt table. Reserved vectors
* will never be triggered, so having them is perfectly safe.
*/

3
include/libopencm3/lm4f/rcc.h
View File

@ -6,7 +6,8 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012
Alexandru Gagniuc <mr.nuke.me@gmail.com>
@date 10 March 2013

9
include/libopencm3/lm4f/systemcontrol.h
View File

@ -6,7 +6,8 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012
Alexandru Gagniuc <mr.nuke.me@gmail.com>
@date 10 March 2013
@ -726,9 +727,9 @@ typedef enum {
} clken_t;
/* =============================================================================
/* ============================================================================
* Function prototypes
* ---------------------------------------------------------------------------*/
* --------------------------------------------------------------------------*/
BEGIN_DECLS
void periph_clock_enable(clken_t periph);
@ -740,5 +741,3 @@ END_DECLS
#endif /* LM4F_SYSTEMCONTROL_H */

15
include/libopencm3/lm4f/uart.h
View File

@ -6,7 +6,8 @@
*
* @version 1.0.0
*
* @author @htmlonly &copy; @endhtmlonly 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
* @author @htmlonly &copy; @endhtmlonly 2013
* Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* @date 07 May 2013
*
@ -479,7 +480,8 @@ void uart_set_fifo_trigger_levels(u32 uart,
* @param[in] uart UART block register address base @ref uart_reg_base
*/
static inline
bool uart_is_tx_fifo_full(u32 uart) {
bool uart_is_tx_fifo_full(u32 uart)
{
return UART_FR(uart) & UART_FR_TXFF;
}
@ -490,7 +492,8 @@ bool uart_is_tx_fifo_full(u32 uart) {
* @param[in] uart UART block register address base @ref uart_reg_base
*/
static inline
bool uart_is_tx_fifo_empty(u32 uart) {
bool uart_is_tx_fifo_empty(u32 uart)
{
return UART_FR(uart) & UART_FR_TXFE;
}
@ -500,7 +503,8 @@ bool uart_is_tx_fifo_empty(u32 uart) {
* @param[in] uart UART block register address base @ref uart_reg_base
*/
static inline
bool uart_is_rx_fifo_full(u32 uart) {
bool uart_is_rx_fifo_full(u32 uart)
{
return UART_FR(uart) & UART_FR_RXFF;
}
@ -510,7 +514,8 @@ bool uart_is_rx_fifo_full(u32 uart) {
* @param[in] uart UART block register address base @ref uart_reg_base
*/
static inline
bool uart_is_rx_fifo_empty(u32 uart) {
bool uart_is_rx_fifo_empty(u32 uart)
{
return UART_FR(uart) & UART_FR_RXFE;
}
/**@}*/

40
include/libopencm3/lm4f/usb.h
View File

@ -41,15 +41,15 @@
#include <libopencm3/lm4f/memorymap.h>
#include <libopencm3/cm3/common.h>
/* =============================================================================
/* ============================================================================
* USB registers
* ---------------------------------------------------------------------------*/
* --------------------------------------------------------------------------*/
/* USB Device Functional Address */
#define USB_FADDR MMIO8 (USB_BASE + 0x00)
#define USB_FADDR MMIO8(USB_BASE + 0x00)
/* USB Power */
#define USB_POWER MMIO8 (USB_BASE + 0x01)
#define USB_POWER MMIO8(USB_BASE + 0x01)
/* USB Transmit Interrupt Status */
#define USB_TXIS MMIO16(USB_BASE + 0x02)
@ -64,19 +64,19 @@
#define USB_RXIE MMIO16(USB_BASE + 0x08)
/* USB General Interrupt Status */
#define USB_IS MMIO8 (USB_BASE + 0x0A)
#define USB_IS MMIO8(USB_BASE + 0x0A)
/* USB Interrupt Enable */
#define USB_IE MMIO8 (USB_BASE + 0x0B)
#define USB_IE MMIO8(USB_BASE + 0x0B)
/* USB Frame Value */
#define USB_FRAME MMIO16(USB_BASE + 0x0C)
/* USB Endpoint Index */
#define USB_EPIDX MMIO8 (USB_BASE + 0x0E)
#define USB_EPIDX MMIO8(USB_BASE + 0x0E)
/* USB Test Mode */
#define USB_TEST MMIO8 (USB_BASE + 0x0F)
#define USB_TEST MMIO8(USB_BASE + 0x0F)
/* USB FIFO Endpoint [0-7] */
#define USB_FIFO8(n) MMIO8(USB_BASE + 0x20 + n*0x04)
@ -84,10 +84,10 @@
#define USB_FIFO32(n) MMIO32(USB_BASE + 0x20 + n*0x04)
/* USB Transmit Dynamic FIFO Sizing */
#define USB_TXFIFOSZ MMIO8 (USB_BASE + 0x62)
#define USB_TXFIFOSZ MMIO8(USB_BASE + 0x62)
/* USB Receive Dynamic FIFO Sizing */
#define USB_RXFIFOSZ MMIO8 (USB_BASE + 0x63)
#define USB_RXFIFOSZ MMIO8(USB_BASE + 0x63)
/* USB Transmit FIFO Start Address */
#define USB_TXFIFOADD MMIO16(USB_BASE + 0x64)
@ -96,40 +96,40 @@
#define USB_RXFIFOADD MMIO16(USB_BASE + 0x66)
/* USB Connect Timing */
#define USB_CONTIM MMIO8 (USB_BASE + 0x7A)
#define USB_CONTIM MMIO8(USB_BASE + 0x7A)
/* USB Full-Speed Last Transaction to End of Frame Timing */
#define USB_FSEOF MMIO8 (USB_BASE + 0x7D)
#define USB_FSEOF MMIO8(USB_BASE + 0x7D)
/* USB Low-Speed Last Transaction to End of Frame Timing */
#define USB_LSEOF MMIO8 (USB_BASE + 0x7E)
#define USB_LSEOF MMIO8(USB_BASE + 0x7E)
/* USB Control and Status Endpoint 0 Low */
#define USB_CSRL0 MMIO8 (USB_BASE + 0x102)
#define USB_CSRL0 MMIO8(USB_BASE + 0x102)
/* USB Control and Status Endpoint 0 High */
#define USB_CSRH0 MMIO8 (USB_BASE + 0x103)
#define USB_CSRH0 MMIO8(USB_BASE + 0x103)
/* USB Receive Byte Count Endpoint 0 */
#define USB_COUNT0 MMIO8 (USB_BASE + 0x108)
#define USB_COUNT0 MMIO8(USB_BASE + 0x108)
/* USB Maximum Transmit Data Endpoint [1-7] */
#define USB_TXMAXP(n) MMIO16(USB_BASE + 0x100 + n*0x10)
/* USB Transmit Control and Status Endpoint [1-7] Low */
#define USB_TXCSRL(n) MMIO8 (USB_BASE + 0x102 + n*0x10)
#define USB_TXCSRL(n) MMIO8(USB_BASE + 0x102 + n*0x10)
/* USB Transmit Control and Status Endpoint [1-7] High */
#define USB_TXCSRH(n) MMIO8 (USB_BASE + 0x103 + n*0x10)
#define USB_TXCSRH(n) MMIO8(USB_BASE + 0x103 + n*0x10)
/* USB Maximum Receive Data Endpoint [1-7] */
#define USB_RXMAXP(n) MMIO16(USB_BASE + 0x104 + n*0x10)
/* USB Receive Control and Status Endpoint [1-7] Low */
#define USB_RXCSRL(n) MMIO8 (USB_BASE + 0x106 + n*0x10)
#define USB_RXCSRL(n) MMIO8(USB_BASE + 0x106 + n*0x10)
/* USB Receive Control and Status Endpoint [1-7] High */
#define USB_RXCSRH(n) MMIO8 (USB_BASE + 0x107 + n*0x10)
#define USB_RXCSRH(n) MMIO8(USB_BASE + 0x107 + n*0x10)
/* USB Receive Byte Count Endpoint [1-7] */
#define USB_RXCOUNT(n) MMIO16(USB_BASE + 0x108 + n*0x10)

3
include/libopencm3/lpc43xx/creg.h
View File

@ -1,6 +1,7 @@
/** @defgroup creg_defines Configuration Registers Defines
@brief <b>Defined Constants and Types for the LPC43xx Configuration Registers</b>
@brief <b>Defined Constants and Types for the LPC43xx Configuration
Registers</b>
@ingroup LPC43xx_defines

3
include/libopencm3/lpc43xx/gima.h
View File

@ -1,6 +1,7 @@
/** @defgroup gima_defines Global Input Multiplexer Array Defines
@brief <b>Defined Constants and Types for the LPC43xx Global Input Multiplexer Array</b>
@brief <b>Defined Constants and Types for the LPC43xx Global Input Multiplexer
Array</b>
@ingroup LPC43xx_defines

4
include/libopencm3/lpc43xx/gpio.h
View File

@ -88,7 +88,7 @@ LGPL License Terms @ref lgpl_license
/* --- GPIO registers ------------------------------------------------------ */
//TODO byte/word access registers
/* TODO byte/word access registers */
/* GPIO data direction register (GPIOn_DIR) */
#define GPIO_DIR(port) MMIO32(port + 0x00)
@ -167,7 +167,7 @@ LGPL License Terms @ref lgpl_license
#define GPIO6_NOT GPIO_NOT(GPIO6)
#define GPIO7_NOT GPIO_NOT(GPIO7)
//TODO interrupts
/* TODO interrupts */
BEGIN_DECLS

1
include/libopencm3/lpc43xx/i2s.h
View File

@ -45,7 +45,6 @@ LGPL License Terms @ref lgpl_license
#define I2S0 I2S0_BASE
#define I2S1 I2S1_BASE
/* --- I2S registers ------------------------------------------------------- */
/* I2S Digital Audio Output Register */

3
include/libopencm3/lpc43xx/ritimer.h
View File

@ -1,6 +1,7 @@
/** @defgroup ritimer_defines Repetitive Interrupt Timer Defines
@brief <b>Defined Constants and Types for the LPC43xx Repetitive Interrupt Timer</b>
@brief <b>Defined Constants and Types for the LPC43xx Repetitive Interrupt
Timer</b>
@ingroup LPC43xx_defines

64
include/libopencm3/lpc43xx/scu.h
View File

@ -406,12 +406,13 @@ LGPL License Terms @ref lgpl_license
#define SCU_I2C0_NOMINAL (SCU_SCL_EZI_EN | SCU_SDA_EZI_EN)
/* Standard mode for I2C SCL/SDA Fast-mode Plus transmit */
#define SCU_I2C0_FAST (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | SCU_SCL_ZIF_DIS \
SCU_SDA_EFP | SCU_SDA_EHD | SCU_SDA_EZI_EN)
#define SCU_I2C0_FAST (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | \
SCU_SCL_ZIF_DIS | SCU_SDA_EFP | SCU_SDA_EHD | \
SCU_SDA_EZI_EN)
/*
* SCU PIN Normal Drive:
* The pin configuration registers for normal-drive pins control the following pins:
* The configuration registers for normal-drive pins control the following pins:
* - P0_0 and P0_1
* - P1_0 to P1_16 and P1_18 to P1_20
* - P2_0 to P2_2 and P2_6 to P2_13
@ -429,7 +430,7 @@ LGPL License Terms @ref lgpl_license
* - PF_0 to PF_11
*
* Pin configuration registers for High-Drive pins.
* The pin configuration registers for high-drive pins control the following pins:
* The configuration registers for high-drive pins control the following pins:
* - P1_17
* - P2_3 to P2_5
* - P8_0 to P8_2
@ -607,7 +608,9 @@ typedef enum {
PC_13 = (PIN_GROUPC+PIN13),
PC_14 = (PIN_GROUPC+PIN14),
/* Group Port D (seems not configurable through SCU, not defined in UM10503.pdf Rev.1, keep it here) */
/* Group Port D (seems not configurable through SCU, not defined in
* UM10503.pdf Rev.1, keep it here)
*/
PD_0 = (PIN_GROUPD+PIN0),
PD_1 = (PIN_GROUPD+PIN1),
PD_2 = (PIN_GROUPD+PIN2),
@ -700,21 +703,23 @@ typedef enum {
/*
* Select Slew Rate.
* By Default=0 Slow.
* Available to normal-drive pins and high-speed pins, reserved for high-drive pins.
* Available to normal-drive and high-speed pins, reserved for high-drive pins.
*/
#define SCU_CONF_EHS_FAST (BIT5)
/*
* Input buffer enable.
* By Default=0 Disable Input Buffer.
* The input buffer is disabled by default at reset and must be enabled.
* for receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer to the pad(in high-drive pins).
* The input buffer is disabled by default at reset and must be enabled for
* receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer
* to the pad(in high-drive pins).
* Available to normal-drive pins, high-drive pins, high-speed pins.
*/
#define SCU_CONF_EZI_EN_IN_BUFFER (BIT6)
/*
* Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.
* Input glitch filter. Disable the input glitch filter for clocking signals
* higher than 30 MHz.
* Available to normal-drive pins, high-drive pins, high-speed pins.
*/
#define SCU_CONF_ZIF_DIS_IN_GLITCH_FILT (BIT7)
@ -730,16 +735,39 @@ typedef enum {
/* BIT10 to 31 are Reserved */
/* Configuration for different I/O pins types */
#define SCU_EMC_IO (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
#define SCU_LCD (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
#define SCU_CLK_IN (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
#define SCU_CLK_OUT (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
#define SCU_EMC_IO (SCU_CONF_EPD_EN_PULLDOWN | \
SCU_CONF_EHS_FAST | \
SCU_CONF_EZI_EN_IN_BUFFER | \
SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
#define SCU_LCD (SCU_CONF_EPUN_DIS_PULLUP | \
SCU_CONF_EHS_FAST | \
SCU_CONF_EZI_EN_IN_BUFFER | \
SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
#define SCU_CLK_IN (SCU_CONF_EPD_EN_PULLDOWN | \
SCU_CONF_EHS_FAST | \
SCU_CONF_EZI_EN_IN_BUFFER | \
SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
#define SCU_CLK_OUT (SCU_CONF_EPD_EN_PULLDOWN | \
SCU_CONF_EHS_FAST | \
SCU_CONF_EZI_EN_IN_BUFFER | \
SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
#define SCU_GPIO_PUP (SCU_CONF_EZI_EN_IN_BUFFER)
#define SCU_GPIO_PDN (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER)
#define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EZI_EN_IN_BUFFER)
#define SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
#define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER)
#define SCU_SSP_IO (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
#define SCU_GPIO_PDN (SCU_CONF_EPUN_DIS_PULLUP | \
SCU_CONF_EPD_EN_PULLDOWN | \
SCU_CONF_EZI_EN_IN_BUFFER)
#define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | \
SCU_CONF_EZI_EN_IN_BUFFER)
#define SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | \
SCU_CONF_EHS_FAST | \
SCU_CONF_EZI_EN_IN_BUFFER | \
SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
#define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | \
SCU_CONF_EPD_EN_PULLDOWN | \
SCU_CONF_EZI_EN_IN_BUFFER)
#define SCU_SSP_IO (SCU_CONF_EPUN_DIS_PULLUP | \
SCU_CONF_EHS_FAST | \
SCU_CONF_EZI_EN_IN_BUFFER | \
SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
BEGIN_DECLS

24
include/libopencm3/lpc43xx/sgpio.h
View File

@ -1,6 +1,7 @@
/** @defgroup sgpio_defines Serial General Purpose I/O
@brief <b>Defined Constants and Types for the LPC43xx Serial General Purpose I/O</b>
@brief <b>Defined Constants and Types for the LPC43xx Serial General Purpose
I/O</b>
@ingroup LPC43xx_defines
@ -76,7 +77,8 @@ LGPL License Terms @ref lgpl_license
#define SGPIO_OUT_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0x3C)
/* SGPIO multiplexer configuration registers (SGPIO_MUX_CFG0 to 15) */
#define SGPIO_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x40 + (slice * 0x04))
#define SGPIO_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x40 + \
(slice * 0x04))
#define SGPIO_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x40)
#define SGPIO_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x44)
#define SGPIO_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x48)
@ -95,7 +97,8 @@ LGPL License Terms @ref lgpl_license
#define SGPIO_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0x7C)
/* Slice multiplexer configuration registers (SLICE_MUX_CFG0 to 15) */
#define SGPIO_SLICE_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x80 + (slice * 0x04))
#define SGPIO_SLICE_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x80 + \
(slice * 0x04))
#define SGPIO_SLICE_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x80)
#define SGPIO_SLICE_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x84)
#define SGPIO_SLICE_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x88)
@ -114,7 +117,8 @@ LGPL License Terms @ref lgpl_license
#define SGPIO_SLICE_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0xBC)
/* Slice data registers (REG0 to 15) */
#define SGPIO_REG(slice) MMIO32(SGPIO_PORT_BASE + 0xC0 + (slice * 0x04))
#define SGPIO_REG(slice) MMIO32(SGPIO_PORT_BASE + 0xC0 + \
(slice * 0x04))
#define SGPIO_REG0 MMIO32(SGPIO_PORT_BASE + 0xC0)
#define SGPIO_REG1 MMIO32(SGPIO_PORT_BASE + 0xC4)
#define SGPIO_REG2 MMIO32(SGPIO_PORT_BASE + 0xC8)
@ -133,7 +137,8 @@ LGPL License Terms @ref lgpl_license
#define SGPIO_REG15 MMIO32(SGPIO_PORT_BASE + 0xFC)
/* Slice data shadow registers (REG_SS0 to 15) */
#define SGPIO_REG_SS(slice) MMIO32(SGPIO_PORT_BASE + 0x100 + (slice * 0x04))
#define SGPIO_REG_SS(slice) MMIO32(SGPIO_PORT_BASE + 0x100 + \
(slice * 0x04))
#define SGPIO_REG_SS0 MMIO32(SGPIO_PORT_BASE + 0x100)
#define SGPIO_REG_SS1 MMIO32(SGPIO_PORT_BASE + 0x104)
#define SGPIO_REG_SS2 MMIO32(SGPIO_PORT_BASE + 0x108)
@ -152,7 +157,8 @@ LGPL License Terms @ref lgpl_license
#define SGPIO_REG_SS15 MMIO32(SGPIO_PORT_BASE + 0x13C)
/* Reload registers (PRESET0 to 15) */
#define SGPIO_PRESET(slice) MMIO32(SGPIO_PORT_BASE + 0x140 + (slice * 0x04))
#define SGPIO_PRESET(slice) MMIO32(SGPIO_PORT_BASE + 0x140 + \
(slice * 0x04))
#define SGPIO_PRESET0 MMIO32(SGPIO_PORT_BASE + 0x140)
#define SGPIO_PRESET1 MMIO32(SGPIO_PORT_BASE + 0x144)
#define SGPIO_PRESET2 MMIO32(SGPIO_PORT_BASE + 0x148)
@ -171,7 +177,8 @@ LGPL License Terms @ref lgpl_license
#define SGPIO_PRESET15 MMIO32(SGPIO_PORT_BASE + 0x17C)
/* Down counter registers (COUNT0 to 15) */
#define SGPIO_COUNT(slice) MMIO32(SGPIO_PORT_BASE + 0x180 + (slice * 0x04))
#define SGPIO_COUNT(slice) MMIO32(SGPIO_PORT_BASE + 0x180 + \
(slice * 0x04))
#define SGPIO_COUNT0 MMIO32(SGPIO_PORT_BASE + 0x180)
#define SGPIO_COUNT1 MMIO32(SGPIO_PORT_BASE + 0x184)
#define SGPIO_COUNT2 MMIO32(SGPIO_PORT_BASE + 0x188)
@ -190,7 +197,8 @@ LGPL License Terms @ref lgpl_license
#define SGPIO_COUNT15 MMIO32(SGPIO_PORT_BASE + 0x1BC)
/* Position registers (POS0 to 15) */
#define SGPIO_POS(slice) MMIO32(SGPIO_PORT_BASE + 0x1C0 + (slice * 0x04))
#define SGPIO_POS(slice) MMIO32(SGPIO_PORT_BASE + 0x1C0 + \
(slice * 0x04))
#define SGPIO_POS0 MMIO32(SGPIO_PORT_BASE + 0x1C0)
#define SGPIO_POS1 MMIO32(SGPIO_PORT_BASE + 0x1C4)
#define SGPIO_POS2 MMIO32(SGPIO_PORT_BASE + 0x1C8)

14
include/libopencm3/lpc43xx/ssp.h
View File

@ -1,6 +1,7 @@
/** @defgroup ssp_defines Synchronous Serial Port
@brief <b>Defined Constants and Types for the LPC43xx Synchronous Serial Port</b>
@brief <b>Defined Constants and Types for the LPC43xx Synchronous Serial
Port</b>
@ingroup LPC43xx_defines
@ -110,8 +111,8 @@ typedef enum {
} ssp_num_t;
/*
* SSP Control Register 0
*/
* SSP Control Register 0
*/
/* SSP Data Size Bits 0 to 3 */
typedef enum {
SSP_DATA_4BITS = 0x3,
@ -145,8 +146,8 @@ typedef enum {
} ssp_cpol_cpha_t;
/*
* SSP Control Register 1
*/
* SSP Control Register 1
*/
/* SSP Mode Bit0 */
typedef enum {
SSP_MODE_NORMAL = 0x0,
@ -180,7 +181,8 @@ void ssp_disable(ssp_num_t ssp_num);
/*
* SSP Init
* clk_prescale shall be in range 2 to 254 (even number only).
* Clock computation: PCLK / (CPSDVSR * [SCR+1]) => CPSDVSR=clk_prescale, SCR=serial_clock_rate
* Clock computation: PCLK / (CPSDVSR * [SCR+1]) => CPSDVSR=clk_prescale,
* SCR=serial_clock_rate
*/
void ssp_init(ssp_num_t ssp_num,
ssp_datasize_t data_size,

2
include/libopencm3/lpc43xx/usb.h
View File

@ -152,6 +152,6 @@
/* --- USB1 registers ------------------------------------------------------ */
//TODO
/* TODO */
#endif

3
include/libopencm3/lpc43xx/wwdt.h
View File

@ -1,6 +1,7 @@
/** @defgroup wwdt_defines Windowed Watchdog Timer
@brief <b>Defined Constants and Types for the LPC43xx Windowed Watchdog Timer</b>
@brief <b>Defined Constants and Types for the LPC43xx Windowed Watchdog
Timer</b>
@ingroup LPC43xx_defines

6
include/libopencm3/stm32/can.h
View File

@ -159,8 +159,10 @@ LGPL License Terms @ref lgpl_license
* Connectivity line devices have 28 banks so the bank ID spans 0..27
* all other devices have 14 banks so the bank ID spans 0..13.
*/
#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x0)
#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x4)
#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + \
(bank * 0x8) + 0x0)
#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + \
(bank * 0x8) + 0x4)
/* --- CAN_MCR values ------------------------------------------------------ */

3
include/libopencm3/stm32/common/dac_common_all.h
View File

@ -1,6 +1,7 @@
/** @addtogroup dac_defines
@author @htmlonly &copy; @endhtmlonly 2012 Felix Held <felix-libopencm3@felixheld.de>
@author @htmlonly &copy; @endhtmlonly 2012
Felix Held <felix-libopencm3@felixheld.de>
*/

49
include/libopencm3/stm32/common/dma_common_f13.h
View File

@ -1,7 +1,9 @@
/** @addtogroup dma_defines
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@author @htmlonly &copy; @endhtmlonly 2012 Piotr Esden-Tempski <piotr@esden.net>
@author @htmlonly &copy; @endhtmlonly 2010
Thomas Otto <tommi@viadmin.org>
@author @htmlonly &copy; @endhtmlonly 2012
Piotr Esden-Tempski <piotr@esden.net>
*/
@ -141,8 +143,11 @@ specific memorymap.h header before including this header file.*/
/* --- DMA_ISR values ------------------------------------------------------ */
/* --- DMA Interrupt Flag offset values ------------------------------------- */
/* These are based on every interrupt flag and flag clear being at the same relative location */
/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within channel flag group.
/* These are based on every interrupt flag and flag clear being at the same
* relative location
*/
/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within channel flag
group.
@ingroup dma_defines
@{*/
@ -156,14 +161,18 @@ specific memorymap.h header before including this header file.*/
#define DMA_GIF (1 << 0)
/**@}*/
/* Offset within interrupt status register to start of channel interrupt flag field */
/* Offset within interrupt status register to start of channel interrupt flag
* field
*/
#define DMA_FLAG_OFFSET(channel) (4*(channel - 1))
#define DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | DMA_GIF)
#define DMA_ISR_MASK(channel) DMA_FLAGS << DMA_FLAG_OFFSET(channel)
#define DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | \
DMA_GIF)
#define DMA_ISR_MASK(channel) (DMA_FLAGS << DMA_FLAG_OFFSET(channel))
/* TEIF: Transfer error interrupt flag */
#define DMA_ISR_TEIF_BIT DMA_TEIF
#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1)
#define DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2)
@ -175,7 +184,8 @@ specific memorymap.h header before including this header file.*/
/* HTIF: Half transfer interrupt flag */
#define DMA_ISR_HTIF_BIT DMA_HTIF
#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1)
#define DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2)
@ -187,7 +197,8 @@ specific memorymap.h header before including this header file.*/
/* TCIF: Transfer complete interrupt flag */
#define DMA_ISR_TCIF_BIT DMA_TCIF
#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1)
#define DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2)
@ -199,7 +210,8 @@ specific memorymap.h header before including this header file.*/
/* GIF: Global interrupt flag */
#define DMA_ISR_GIF_BIT DMA_GIF
#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1)
#define DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2)
@ -213,7 +225,8 @@ specific memorymap.h header before including this header file.*/
/* CTEIF: Transfer error clear */
#define DMA_IFCR_CTEIF_BIT DMA_TEIF
#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1)
#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2)
@ -225,7 +238,8 @@ specific memorymap.h header before including this header file.*/
/* CHTIF: Half transfer clear */
#define DMA_IFCR_CHTIF_BIT DMA_HTIF
#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1)
#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2)
@ -237,7 +251,8 @@ specific memorymap.h header before including this header file.*/
/* CTCIF: Transfer complete clear */
#define DMA_IFCR_CTCIF_BIT DMA_TCIF
#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1)
#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2)
@ -249,7 +264,8 @@ specific memorymap.h header before including this header file.*/
/* CGIF: Global interrupt clear */
#define DMA_IFCR_CGIF_BIT DMA_GIF
#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1)
#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2)
@ -261,7 +277,8 @@ specific memorymap.h header before including this header file.*/
/* Clear interrupts mask */
#define DMA_IFCR_CIF_BIT 0xF
#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << (DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CIF1 DMA_IFCR_CIF(DMA_CHANNEL1)
#define DMA_IFCR_CIF2 DMA_IFCR_CIF(DMA_CHANNEL2)

28
include/libopencm3/stm32/common/dma_common_f24.h
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@ -1,7 +1,9 @@
/** @addtogroup dma_defines
@author @htmlonly &copy; @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2011
Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
*/
/*
@ -152,7 +154,8 @@ specific memorymap.h header before including this header file.*/
#define DMA2_S7NDTR DMA2_SNDTR(7)
/* DMA Stream x peripheral address register (DMA_SxPAR) */
#define DMA_SPAR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x08)
#define DMA_SPAR(port, n) (*(volatile void **)\
(DMA_STREAM(port, n) + 0x08))
#define DMA1_SPAR(n) DMA_SPAR(DMA1, n)
#define DMA2_SPAR(n) DMA_SPAR(DMA2, n)
@ -175,7 +178,8 @@ specific memorymap.h header before including this header file.*/
#define DMA2_S7PAR DMA2_SPAR(7)
/* DMA Stream x memory address 0 register (DMA_SxM0AR) */
#define DMA_SM0AR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x0c)
#define DMA_SM0AR(port, n) (*(volatile void **) \
(DMA_STREAM(port, n) + 0x0c))
#define DMA1_SM0AR(n) DMA_SM0AR(DMA1, n)
#define DMA2_SM0AR(n) DMA_SM0AR(DMA2, n)
@ -198,7 +202,8 @@ specific memorymap.h header before including this header file.*/
#define DMA2_S7M0AR DMA2_SM0AR(7)
/* DMA Stream x memory address 1 register (DMA_SxM1AR) */
#define DMA_SM1AR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x10)
#define DMA_SM1AR(port, n) (*(volatile void **)\
(DMA_STREAM(port, n) + 0x10))
#define DMA1_SM1AR(n) DMA_SM1AR(DMA1, n)
#define DMA2_SM1AR(n) DMA_SM1AR(DMA2, n)
@ -263,10 +268,13 @@ being at the same relative location */
#define DMA_FEIF (1 << 0)
/**@}*/
/* Offset within interrupt status register to start of stream interrupt flag field */
/* Offset within interrupt status register to start of stream interrupt flag
* field
*/
#define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*((stream & 0x02) >> 1))
#define DMA_ISR_FLAGS (DMA_TCIF | DMA_HTIF | DMA_TEIF | DMA_DMEIF | DMA_FEIF)
#define DMA_ISR_MASK(stream) DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream)
#define DMA_ISR_FLAGS (DMA_TCIF | DMA_HTIF | DMA_TEIF | DMA_DMEIF | \
DMA_FEIF)
#define DMA_ISR_MASK(stream) (DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream))
/* --- DMA_LISR values ----------------------------------------------------- */
@ -560,8 +568,8 @@ being at the same relative location */
BEGIN_DECLS
/*
* Note: The F2 and F4 series have a completely new DMA peripheral with different
* configuration options.
* Note: The F2 and F4 series have a completely new DMA peripheral with
* different configuration options.
*/
void dma_stream_reset(u32 dma, u8 stream);

6
include/libopencm3/stm32/common/flash_common_f24.h
View File

@ -22,7 +22,7 @@
* For details see:
* PM0081 Programming manual: STM32F40xxx and STM32F41xxx Flash programming
* September 2011, Doc ID 018520 Rev 1
* http://www.st.com/st-web-ui/static/active/en/resource/technical/document/programming_manual/DM00023388.pdf
* http://goo.gl/3ylKe
*/
/** @cond */
@ -145,7 +145,7 @@ void flash_program_double_word(u32 address, u64 data);
void flash_program_word(u32 address, u32 data);
void flash_program_half_word(u32 address, u16 data);
void flash_program_byte(u32 address, u8 data);
void flash_program(u32 address, u8* data, u32 len);
void flash_program(u32 address, u8 *data, u32 len);
void flash_wait_for_last_operation(void);
void flash_program_option_bytes(u32 data);
@ -154,7 +154,7 @@ END_DECLS
#endif
/** @cond */
#else
#warning "flash_common_f24.h should not be included explicitly, only via flash.h"
#warning "flash_common_f24.h should not be included direcitly, only via flash.h"
#endif
/** @endcond */

8
include/libopencm3/stm32/common/gpio_common_all.h
View File

@ -1,7 +1,9 @@
/** @addtogroup gpio_defines
@author @htmlonly &copy; @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2011
Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
*/
@ -30,7 +32,7 @@ The order of header inclusion is important. gpio.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#if defined (LIBOPENCM3_GPIO_H) || defined (LIBOPENCM3_GPIO_COMMON_F24_H)
#if defined(LIBOPENCM3_GPIO_H) || defined(LIBOPENCM3_GPIO_COMMON_F24_H)
/** @endcond */
#ifndef LIBOPENCM3_GPIO_COMMON_ALL_H
#define LIBOPENCM3_GPIO_COMMON_ALL_H

14
include/libopencm3/stm32/common/gpio_common_f24.h
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@ -1,7 +1,9 @@
/** @addtogroup gpio_defines
@author @htmlonly &copy; @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2011
Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
*/
/*
@ -278,10 +280,10 @@ specific memorymap.h header before including this header file.*/
BEGIN_DECLS
/*
* Note: The F2 and F4 series have a completely new GPIO peripheral with different
* configuration options. Here we implement a different API partly to more
* closely match the peripheral capabilities and also to deliberately break
* compatibility with old F1 code so there is no confusion with similar
* Note: The F2 and F4 series have a completely new GPIO peripheral with
* different configuration options. Here we implement a different API partly to
* more closely match the peripheral capabilities and also to deliberately
* break compatibility with old F1 code so there is no confusion with similar
* sounding functions that have very different functionality.
*/

12
include/libopencm3/stm32/common/hash_common_f24.h
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@ -1,6 +1,7 @@
/** @addtogroup hash_defines
@author @htmlonly &copy; @endhtmlonly 2013 Mikhail Avkhimenia <mikhail@avkhimenia.net>
@author @htmlonly &copy; @endhtmlonly 2013
Mikhail Avkhimenia <mikhail@avkhimenia.net>
*/
@ -54,7 +55,7 @@
#define HASH_STR MMIO32(HASH + 0x08)
/* HASH digest registers (HASH_HR[5]) */
#define HASH_HR ((volatile uint32_t*)(HASH + 0x0C)) //x5
#define HASH_HR ((volatile uint32_t*)(HASH + 0x0C)) /* x5 */
/* HASH interrupt enable register (HASH_IMR) */
#define HASH_IMR MMIO32(HASH + 0x20)
@ -63,7 +64,7 @@
#define HASH_SR MMIO32(HASH + 0x28)
/* HASH context swap registers (HASH_CSR[51]) */
#define HASH_CSR ((volatile uint32_t*)(HASH + 0xF8)) //x51
#define HASH_CSR ((volatile uint32_t*)(HASH + 0xF8)) /* x51 */
/* --- HASH_CR values ------------------------------------------------------ */
@ -127,7 +128,8 @@
/* --- HASH_STR values ----------------------------------------------------- */
/* NBLW: Number of valid bits in the last word of the message in the bit string */
/* NBLW: Number of valid bits in the last word of the message in the bit string
*/
#define HASH_STR_NBW (31 << 0)
/* DCAL: Digest calculation */
@ -155,7 +157,7 @@
/* BUSY: Busy bit */
#define HASH_SR_BUSY (1 << 3)
/* --- HASH function prototypes ------------------------------------------------------- */
/* --- HASH function prototypes -------------------------------------------- */
BEGIN_DECLS

2
include/libopencm3/stm32/common/i2c_common_all.h
View File

@ -28,7 +28,7 @@ The order of header inclusion is important. i2c.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#if defined (LIBOPENCM3_I2C_H) || defined (LIBOPENCM3_I2C_COMMON_F24_H)
#if defined(LIBOPENCM3_I2C_H) || defined(LIBOPENCM3_I2C_COMMON_F24_H)
/** @endcond */
#ifndef LIBOPENCM3_I2C_COMMON_ALL_H
#define LIBOPENCM3_I2C_COMMON_ALL_H

3
include/libopencm3/stm32/common/i2c_common_f24.h
View File

@ -1,6 +1,7 @@
/** @addtogroup i2c_defines
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
*/

76
include/libopencm3/stm32/common/rtc_common_bcd.h
View File

@ -102,7 +102,8 @@ specific memorymap.h header before including this header file.*/
/* RTC time register (RTC_TR) ----------------------------------- */
/* Note: Bits [31:23], 15, and 7 are reserved, and must be kept at reset value. */
/* Note: Bits [31:23], 15, and 7 are reserved, and must be kept at reset value.
*/
#define RTC_TR_PM (1 << 22) /* AM/PM notation */
#define RTC_TR_HT_SHIFT (20) /* Hour tens in BCD format shift */
#define RTC_TR_HT_MASK (0x3) /* Hour tens in BCD format mask */
@ -118,7 +119,8 @@ specific memorymap.h header before including this header file.*/
#define RTC_TR_SU_MASK (0xf) /* Second units in BCD format mask */
/* RTC date register (RTC_DR) ----------------------------------- */
/* Note: Bits [31:24] and [7:6] are reserved, and must be kept at reset value. */
/* Note: Bits [31:24] and [7:6] are reserved, and must be kept at reset value.
*/
#define RTC_DR_YT_SHIFT (20) /* Year tens in BCD format shift */
#define RTC_DR_YT_MASK (0xf) /* Year tens in BCD format mask */
#define RTC_DR_YU_SHIFT (16) /* Year units in BCD format shift */
@ -136,12 +138,18 @@ specific memorymap.h header before including this header file.*/
/* RTC control register (RTC_CR) -------------------------------- */
/* Note: Bits [31:24] are reserved, and must be kept at reset value. */
/* Note: Bits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1). */
/* Note: Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1. */
/* Note: Bits 7, 6 and 4 of this register can be written in initialization mode
* only (RTC_ISR/INITF = 1).
*/
/* Note: Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit
* = 0 and RTC_ISR WUTWF bit = 1.
*/
#define RTC_CR_COE (1<<23) /* RTC_CR_COE: Calibration output enable */
/* RTC_CR_OSEL: Output selection values */
/* Note: These bits are used to select the flag to be routed to AFO_ALARM RTC output */
/* Note: These bits are used to select the flag to be routed to AFO_ALARM RTC
* output
*/
#define RTC_CR_OSEL_SHIFT 21
#define RTC_CR_OSEL_MASK (0x3)
#define RTC_CR_OSEL_DISABLED (0x0)
@ -150,23 +158,34 @@ specific memorymap.h header before including this header file.*/
#define RTC_CR_OSEL_WAKEUP (0x3)
#define RTC_CR_POL (1<<20) /* RTC_CR_POL: Output polarity */
#define RTC_CR_COSEL (1<<19) /* RTC_CR_COSEL: Calibration output selection */
#define RTC_CR_COSEL (1<<19) /* RTC_CR_COSEL: Calibration output
selection */
#define RTC_CR_BKP (1<<18) /* RTC_CR_BKP: Backup */
#define RTC_CR_SUB1H (1<<17) /* RTC_CR_SUB1H: Subtract 1 hour (winter time change) */
#define RTC_CR_ADD1H (1<<16) /* RTC_CR_ADD1H: Add 1 hour (summer time change) */
#define RTC_CR_TSIE (1<<15) /* RTC_CR_TSIE: Timestamp interrupt enable */
#define RTC_CR_WUTIE (1<<14) /* RTC_CR_WUTIE: Wakeup timer interrupt enable */
#define RTC_CR_ALRBIE (1<<13) /* RTC_CR_ALRBIE: Alarm B interrupt enable */
#define RTC_CR_ALRAIE (1<<12) /* RTC_CR_ALRAIE: Alarm A interrupt enable */
#define RTC_CR_SUB1H (1<<17) /* RTC_CR_SUB1H: Subtract 1 hour
(winter time change) */
#define RTC_CR_ADD1H (1<<16) /* RTC_CR_ADD1H: Add 1 hour (summer
time change) */
#define RTC_CR_TSIE (1<<15) /* RTC_CR_TSIE: Timestamp interrupt
enable */
#define RTC_CR_WUTIE (1<<14) /* RTC_CR_WUTIE: Wakeup timer
interrupt enable */
#define RTC_CR_ALRBIE (1<<13) /* RTC_CR_ALRBIE: Alarm B interrupt
enable */
#define RTC_CR_ALRAIE (1<<12) /* RTC_CR_ALRAIE: Alarm A interrupt
enable */
#define RTC_CR_TSE (1<<11) /* RTC_CR_TSE: Time stamp enable */
#define RTC_CR_WUTE (1<<10) /* RTC_CR_WUTE: Wakeup timer enable */
#define RTC_CR_ALRBE (1<<9) /* RTC_CR_ALRBIE: Alarm B enable */
#define RTC_CR_ALRAE (1<<8) /* RTC_CR_ALRAE: Alarm A enable */
#define RTC_CR_DCE (1<<7) /* RTC_CR_DCE: Course digital calibration enable */
#define RTC_CR_DCE (1<<7) /* RTC_CR_DCE: Course digital
calibration enable */
#define RTC_CR_FMT (1<<6) /* RTC_CR_FMT: Hour format */
#define RTC_CR_BYPSHAD (1<<5) /* RTC_CR_BYPSHAD: Bypass the shadow registers */
#define RTC_CR_REFCKON (1<<4) /* RTC_CR_REFCKON: Reference clock detection enable */
#define RTC_CR_TSEDGE (1<<3) /* RTC_CR_TSEDGE: Timestamp event active edge */
#define RTC_CR_BYPSHAD (1<<5) /* RTC_CR_BYPSHAD: Bypass the shadow
registers */
#define RTC_CR_REFCKON (1<<4) /* RTC_CR_REFCKON: Reference clock
detection enable */
#define RTC_CR_TSEDGE (1<<3) /* RTC_CR_TSEDGE: Timestamp event
active edge */
/* RTC_CR_WUCKSEL: Wakeup clock selection */
#define RTC_CR_WUCLKSEL_SHIFT (0)
@ -181,8 +200,9 @@ specific memorymap.h header before including this header file.*/
/* RTC initialization and status register (RTC_ISR) ------------- */
/* Note: Bits [31:17] and [15] are reserved, and must be kept at reset value. */
/* Note: This register is write protected (except for RTC_ISR[13:8] bits). */
#define RTC_ISR_RECALPF (1<<16) /* RECALPF: Recalibration pending flag */
#define RTC_ISR_TAMP3F (1<<15) /* TAMP3F: TAMPER3 detection flag (not available on F4)*/
#define RTC_ISR_RECALPF (1<<16) /* RECALPF: Recalib pending flag */
#define RTC_ISR_TAMP3F (1<<15) /* TAMP3F: TAMPER3 detection flag
(not on F4)*/
#define RTC_ISR_TAMP2F (1<<14) /* TAMP2F: TAMPER2 detection flag */
#define RTC_ISR_TAMP1F (1<<13) /* TAMP1F: TAMPER detection flag */
#define RTC_ISR_TSOVF (1<<12) /* TSOVF: Timestamp overflow flag */
@ -192,21 +212,21 @@ specific memorymap.h header before including this header file.*/
#define RTC_ISR_ALRAF (1<<8) /* ALRAF: Alarm A flag */
#define RTC_ISR_INIT (1<<7) /* INIT: Initialization mode */
#define RTC_ISR_INITF (1<<6) /* INITF: Initialization flag */
#define RTC_ISR_RSF (1<<5) /* RSF: Registers synchronization flag */
#define RTC_ISR_INITS (1<<4) /* INITS: Initialization status flag */
#define RTC_ISR_RSF (1<<5) /* RSF: Registers sync flag */
#define RTC_ISR_INITS (1<<4) /* INITS: Init status flag */
#define RTC_ISR_SHPF (1<<3) /* SHPF: Shift operation pending */
#define RTC_ISR_WUTWF (1<<2) /* WUTWF: Wakeup timer write flag */
#define RTC_ISR_ALRBWF (1<<1) /* ALRBWF: Alarm B write flag */
#define RTC_ISR_ALRAWF (1<<0) /* ALRAWF: Alarm A write flag */
/* RTC prescaler register (RTC_PRER) ---------------------------- */
#define RTC_PRER_PREDIV_A_SHIFT (16) /* Asynchronous prescaler factor shift */
#define RTC_PRER_PREDIV_A_MASK (0x7f) /* Asynchronous prescaler factor mask */
#define RTC_PRER_PREDIV_S_SHIFT (0) /* Synchronous prescaler factor shift */
#define RTC_PRER_PREDIV_S_MASK (0x7fff) /* Synchronous prescaler factor mask */
#define RTC_PRER_PREDIV_A_SHIFT (16) /* Async prescaler factor shift */
#define RTC_PRER_PREDIV_A_MASK (0x7f) /* Async prescaler factor mask */
#define RTC_PRER_PREDIV_S_SHIFT (0) /* Sync prescaler factor shift */
#define RTC_PRER_PREDIV_S_MASK (0x7fff) /* Sync prescaler factor mask */
/* RTC calibration register (RTC_CALIBR) ------------------------ */
// FIXME - TODO
/* FIXME - TODO */
/* RTC Alarm register ------------------------------------------- */
/* Note: Applies to RTC_ALRMAR and RTC_ALRMBR */
@ -234,7 +254,7 @@ specific memorymap.h header before including this header file.*/
#define RTC_ALRMXR_SU_MASK (0xf)
/* RTC shift control register (RTC_SHIFTR) */
// FIXME - TODO
/* FIXME - TODO */
/* RTC time stamp time register (RTC_TSTR) ---------------------- */
#define RTC_TSTR_PM (1<<22)
@ -263,7 +283,7 @@ specific memorymap.h header before including this header file.*/
#define RTC_TSDR_DU_MASK (0xf)
/* RTC calibration register (RTC_CALR) -------------------------- */
// FIXME - TODO
/* FIXME - TODO */
/* RTC tamper and alternate function configuration register (RTC_TAFCR) --- */
#define RTC_TAFCR_ALARMOUTTYPE (1<<18)
@ -304,7 +324,7 @@ specific memorymap.h header before including this header file.*/
#define RTC_TAFCR_TAMP1E (1<<0)
/* RTC alarm X sub second register */
// FIXME - TODO
/* FIXME - TODO */

2
include/libopencm3/stm32/common/spi_common_all.h
View File

@ -28,7 +28,7 @@ The order of header inclusion is important. spi.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#if defined (LIBOPENCM3_SPI_H) || defined (LIBOPENCM3_SPI_COMMON_F24_H)
#if defined(LIBOPENCM3_SPI_H) || defined(LIBOPENCM3_SPI_COMMON_F24_H)
/** @endcond */
#ifndef LIBOPENCM3_SPI_COMMON_ALL_H
#define LIBOPENCM3_SPI_COMMON_ALL_H

28
include/libopencm3/stm32/common/timer_common_all.h
View File

@ -30,7 +30,7 @@ The order of header inclusion is important. timer.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#if defined (LIBOPENCM3_TIMER_H) || defined (LIBOPENCM3_TIMER_COMMON_F24_H)
#if defined(LIBOPENCM3_TIMER_H) || defined(LIBOPENCM3_TIMER_COMMON_F24_H)
/** @endcond */
#ifndef LIBOPENCM3_TIMER_COMMON_H
#define LIBOPENCM3_TIMER_COMMON_H
@ -434,14 +434,19 @@ level. */
/** Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the complementary input. */
#define TIM_SMCR_SMS_EM3 (0x3 << 0)
/** Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers. */
/** Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes
* the counter and generates an update of the registers.
*/
#define TIM_SMCR_SMS_RM (0x4 << 0)
/** Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. */
/** Gated Mode - The counter clock is enabled when the trigger input (TRGI) is
* high.
*/
#define TIM_SMCR_SMS_GM (0x5 << 0)
/** Trigger Mode - The counter starts at a rising edge of the trigger TRGI. */
#define TIM_SMCR_SMS_TM (0x6 << 0)
/** External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. */
/** External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock
* the counter.
*/
#define TIM_SMCR_SMS_ECM1 (0x7 << 0)
#define TIM_SMCR_SMS_MASK (0x7 << 0)
/**@}*/
@ -936,7 +941,7 @@ and generates an update of the registers. */
/** Output Compare channel designators */
enum tim_oc_id {
TIM_OC1=0,
TIM_OC1 = 0,
TIM_OC1N,
TIM_OC2,
TIM_OC2N,
@ -968,8 +973,8 @@ enum tim_ic_id {
/** Input Capture input filter. The frequency used to sample the
input and the number of events needed to validate an output transition.
TIM_IC_CK_INT_N_x No division from the Deadtime and Sampling Clock frequency (DTF),
filter length x
TIM_IC_CK_INT_N_x No division from the Deadtime and Sampling Clock frequency
(DTF), filter length x
TIM_IC_DTF_DIV_y_N_x Division by y from the DTF, filter length x
*/
enum tim_ic_filter {
@ -1020,7 +1025,7 @@ enum tim_et_pol {
TIM_ET_FALLING,
};
/* --- TIM function prototypes ------------------------------------------------------- */
/* --- TIM function prototypes --------------------------------------------- */
BEGIN_DECLS
@ -1064,7 +1069,8 @@ void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id, enum tim_oc_mode oc_mode);
void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
enum tim_oc_mode oc_mode);
void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id);
@ -1109,7 +1115,7 @@ END_DECLS
#endif
/** @cond */
#else
#warning "timer_common_all.h should not be included explicitly, only via timer.h"
#warning "timer_common_all.h should not be included directly, only via timer.h"
#endif
/** @endcond */
/**@}*/

2
include/libopencm3/stm32/common/timer_common_f24.h
View File

@ -106,7 +106,7 @@ END_DECLS
#endif
/** @cond */
#else
#warning "timer_common_f24.h should not be included explicitly, only via timer.h"
#warning "timer_common_f24.h should not be included directly, only via timer.h"
#endif
/** @endcond */

8
include/libopencm3/stm32/common/usart_common_all.h
View File

@ -30,7 +30,7 @@ The order of header inclusion is important. usart.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#if defined (LIBOPENCM3_USART_H) || defined (LIBOPENCM3_USART_COMMON_F24_H)
#if defined(LIBOPENCM3_USART_H) || defined(LIBOPENCM3_USART_COMMON_F24_H)
/** @endcond */
#ifndef LIBOPENCM3_USART_COMMON_ALL_H
#define LIBOPENCM3_USART_COMMON_ALL_H
@ -324,9 +324,9 @@ specific memorymap.h header before including this header file.*/
@{*/
#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */
#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */
#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* .5 stop bit */
#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */
#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */
#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bit*/
/**@}*/
/* CR3_CTSE/CR3_RTSE combined values */
@ -378,7 +378,7 @@ END_DECLS
#endif
/** @cond */
#else
#warning "usart_common_all.h should not be included explicitly, only via usart.h"
#warning "usart_common_all.h should not be included directly, only via usart.h"
#endif
/** @endcond */
/**@}*/

2
include/libopencm3/stm32/common/usart_common_f24.h
View File

@ -76,7 +76,7 @@ specific memorymap.h header before including this header file.*/
#endif
/** @cond */
#else
#warning "usart_common_f24.h should not be included explicitly, only via usart.h"
#warning "usart_common_f24.h should not be included directly, only via usart.h"
#endif
/** @endcond */

27
include/libopencm3/stm32/f1/adc.h
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@ -1,12 +1,14 @@
/** @defgroup adc_defines ADC Defines
@brief <b>Defined Constants and Types for the STM32F1xx Analog to Digital Converters</b>
@brief <b>Defined Constants and Types for the STM32F1xx Analog to Digital
Converters</b>
@ingroup STM32F1xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
@author @htmlonly &copy; @endhtmlonly 2009
Edward Cheeseman <evbuilder@users.sourceforge.net>
@date 18 August 2012
@ -404,7 +406,8 @@ LGPL License Terms @ref lgpl_license
/* The following are only valid for ADC1 and ADC2. */
/****************************************************************************/
/* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC1 and ADC2 */
/** @defgroup adc_trigger_injected_12 ADC Injected Trigger Identifier for ADC1 and ADC2
/** @defgroup adc_trigger_injected_12 ADC Injected Trigger Identifier for ADC1
and ADC2
@ingroup adc_defines
@{*/
@ -677,7 +680,8 @@ void adc_reset_calibration(u32 adc);
void adc_calibration(u32 adc);
void adc_set_continuous_conversion_mode(u32 adc);
void adc_set_single_conversion_mode(u32 adc);
void adc_on(u32 adc) LIBOPENCM3_DEPRECATED("will be removed in the first release");
void adc_on(u32 adc)
LIBOPENCM3_DEPRECATED("will be removed in the first release");
void adc_off(u32 adc);
void adc_set_sample_time(u32 adc, u8 channel, u8 time);
void adc_set_sample_time_on_all_channels(u32 adc, u8 time);
@ -686,11 +690,16 @@ void adc_set_watchdog_low_threshold(u32 adc, u16 threshold);
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]);
void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]);
void adc_set_continous_conversion_mode(u32 adc) LIBOPENCM3_DEPRECATED("change to adc_set_continuous_conversion_mode");
void adc_set_conversion_time(u32 adc, u8 channel, u8 time) LIBOPENCM3_DEPRECATED("change to adc_set_sample_time");
void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) LIBOPENCM3_DEPRECATED("change to adc_set_sample_time_on_all_channels");
void adc_enable_jeoc_interrupt(u32 adc) LIBOPENCM3_DEPRECATED("change to adc_enable_eoc_interrupt_injected");
void adc_disable_jeoc_interrupt(u32 adc) LIBOPENCM3_DEPRECATED("change to adc_disable_eoc_interrupt_injected");
void adc_set_continous_conversion_mode(u32 adc)
LIBOPENCM3_DEPRECATED("change to adc_set_continuous_conversion_mode");
void adc_set_conversion_time(u32 adc, u8 channel, u8 time)
LIBOPENCM3_DEPRECATED("change to adc_set_sample_time");
void adc_set_conversion_time_on_all_channels(u32 adc, u8 time)
LIBOPENCM3_DEPRECATED("change to adc_set_sample_time_on_all_channels");
void adc_enable_jeoc_interrupt(u32 adc)
LIBOPENCM3_DEPRECATED("change to adc_enable_eoc_interrupt_injected");
void adc_disable_jeoc_interrupt(u32 adc)
LIBOPENCM3_DEPRECATED("change to adc_disable_eoc_interrupt_injected");
END_DECLS
#endif

3
include/libopencm3/stm32/f1/crc.h
View File

@ -1,6 +1,7 @@
/** @defgroup crc_defines CRC Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32F1xx CRC Generator </b>
@brief <b>libopencm3 Defined Constants and Types for the STM32F1xx CRC
Generator </b>
@ingroup STM32F1xx_defines

2
include/libopencm3/stm32/f1/flash.h
View File

@ -22,7 +22,7 @@
* For details see:
* PM0075 programming manual: STM32F10xxx Flash programming
* August 2010, Doc ID 17863 Rev 1
* http://www.st.com/st-web-ui/static/active/en/resource/technical/document/programming_manual/CD00283419.pdf
* http://goo.gl/MuTiU
*/
#ifndef LIBOPENCM3_FLASH_H

93
include/libopencm3/stm32/f1/gpio.h
View File

@ -729,28 +729,28 @@ Line Devices only
@ingroup gpio_defines
@{*/
/* PTP_PPS_REMAP: *//** Ethernet PTP PPS remapping
* (only connectivity line devices) */
/* PTP_PPS_REMAP: */
/** Ethernet PTP PPS remapping (only connectivity line devices) */
#define AFIO_MAPR_PTP_PPS_REMAP (1 << 30)
/* TIM2ITR1_IREMAP: *//** TIM2 internal trigger 1 remapping
* (only connectivity line devices) */
/* TIM2ITR1_IREMAP: */
/** TIM2 internal trigger 1 remapping (only connectivity line devices) */
#define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29)
/* SPI3_REMAP: *//** SPI3/I2S3 remapping
* (only connectivity line devices) */
/* SPI3_REMAP: */
/** SPI3/I2S3 remapping (only connectivity line devices) */
#define AFIO_MAPR_SPI3_REMAP (1 << 28)
/* MII_REMAP: */ /** MII or RMII selection
* (only connectivity line devices) */
/* MII_REMAP: */
/** MII or RMII selection (only connectivity line devices) */
#define AFIO_MAPR_MII_RMII_SEL (1 << 23)
/* CAN2_REMAP: */ /** CAN2 I/O remapping
* (only connectivity line devices) */
/* CAN2_REMAP: */
/** CAN2 I/O remapping (only connectivity line devices) */
#define AFIO_MAPR_CAN2_REMAP (1 << 22)
/* ETH_REMAP: */ /** Ethernet MAC I/O remapping
* (only connectivity line devices) */
/* ETH_REMAP: */
/** Ethernet MAC I/O remapping (only connectivity line devices) */
#define AFIO_MAPR_ETH_REMAP (1 << 21)
/**@}*/
@ -777,41 +777,60 @@ Line Devices only
@ingroup gpio_defines
@{*/
/* ADC2_ETRGREG_REMAP: */ /** ADC2 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
/* ADC2_ETRGREG_REMAP: */
/**
* ADC2 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices)
*/
#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20)
/* ADC2_ETRGINJ_REMAP: */ /** ADC2 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
/* ADC2_ETRGINJ_REMAP: */
/**
* ADC2 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices)
*/
#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19)
/* ADC1_ETRGREG_REMAP: */ /** ADC1 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
/* ADC1_ETRGREG_REMAP: */
/**
* ADC1 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices)
*/
#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18)
/* ADC1_ETRGINJ_REMAP: */ /** ADC1 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
/* ADC1_ETRGINJ_REMAP: */
/**
* ADC1 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices)
*/
#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17)
/* TIM5CH4_IREMAP: */ /** TIM5 channel4 internal remap */
/* TIM5CH4_IREMAP: */
/** TIM5 channel4 internal remap */
#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16)
/* PD01_REMAP: */ /** Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
/* PD01_REMAP: */
/** Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
#define AFIO_MAPR_PD01_REMAP (1 << 15)
/* TIM4_REMAP: */ /** TIM4 remapping */
/* TIM4_REMAP: */
/** TIM4 remapping */
#define AFIO_MAPR_TIM4_REMAP (1 << 12)
/* USART2_REMAP[1:0]: */ /** USART2 remapping */
/* USART2_REMAP[1:0]: */
/** USART2 remapping */
#define AFIO_MAPR_USART2_REMAP (1 << 3)
/* USART1_REMAP[1:0]: */ /** USART1 remapping */
/* USART1_REMAP[1:0]: */
/** USART1 remapping */
#define AFIO_MAPR_USART1_REMAP (1 << 2)
/* I2C1_REMAP[1:0]: */ /** I2C1 remapping */
/* I2C1_REMAP[1:0]: */
/** I2C1 remapping */
#define AFIO_MAPR_I2C1_REMAP (1 << 1)
/* SPI1_REMAP[1:0]: */ /** SPI1 remapping */
/* SPI1_REMAP[1:0]: */
/** SPI1 remapping */
#define AFIO_MAPR_SPI1_REMAP (1 << 0)
/**@}*/
@ -821,7 +840,7 @@ Line Devices only
@{*/
#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13)
#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not on 36pin pkg */
#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not 36pin pkg */
#define AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13)
/**@}*/
@ -870,22 +889,28 @@ Line Devices only
@ingroup gpio_defines
@{*/
/* FSMC_NADV_DISCONNECT: */ /** The NADV is disconnected from its allocated pin */
/* FSMC_NADV_DISCONNECT: */
/** The NADV is disconnected from its allocated pin */
#define AFIO_MAPR2_FSMC_NADV_DISCONNECT (1 << 10)
/* TIM14_REMAP: */ /** TIM14 remapping */
/* TIM14_REMAP: */
/** TIM14 remapping */
#define AFIO_MAPR2_TIM14_REMAP (1 << 9)
/* TIM13_REMAP: */ /** TIM13 remapping */
/* TIM13_REMAP: */
/** TIM13 remapping */
#define AFIO_MAPR2_TIM13_REMAP (1 << 8)
/* TIM11_REMAP: */ /** TIM11 remapping */
/* TIM11_REMAP: */
/** TIM11 remapping */
#define AFIO_MAPR2_TIM11_REMAP (1 << 7)
/* TIM10_REMAP: */ /** TIM10 remapping */
/* TIM10_REMAP: */
/** TIM10 remapping */
#define AFIO_MAPR2_TIM10_REMAP (1 << 6)
/* TIM9_REMAP: */ /** TIM9 remapping */
/* TIM9_REMAP: */
/** TIM9 remapping */
#define AFIO_MAPR2_TIM9_REMAP (1 << 5)
/**@}*/

3
include/libopencm3/stm32/f1/iwdg.h
View File

@ -1,6 +1,7 @@
/** @defgroup iwdg_defines IWDG Defines
@brief <b>Defined Constants and Types for the STM32F1xx Independent Watchdog Timer</b>
@brief <b>Defined Constants and Types for the STM32F1xx Independent Watchdog
Timer</b>
@ingroup STM32F1xx_defines

21
include/libopencm3/stm32/f1/rcc.h
View File

@ -6,8 +6,10 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2009
Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
@author @htmlonly &copy; @endhtmlonly 2009
Uwe Hermann <uwe@hermann-uwe.de>
@date 18 August 2012
@ -55,8 +57,8 @@ LGPL License Terms @ref lgpl_license
#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c)
#define RCC_BDCR MMIO32(RCC_BASE + 0x20)
#define RCC_CSR MMIO32(RCC_BASE + 0x24)
#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /* (**) */
#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /* (**) */
#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /*(**)*/
#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /*(**)*/
/* --- RCC_CR values ------------------------------------------------------- */
@ -125,9 +127,10 @@ LGPL License Terms @ref lgpl_license
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb /* (XX) */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc /* (XX) */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd /* 0xd: PLL x 15 */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn. line */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn.
line */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */
// #define PLLMUL_PLL_CLK_MUL16 0xf /* (XX) */ /* Errata? 17? */
/* #define PLLMUL_PLL_CLK_MUL16 0xf */ /* (XX) */ /* Errata? 17? */
/**@}*/
/* TODO: conn. line differs. */
@ -286,7 +289,8 @@ LGPL License Terms @ref lgpl_license
#define RCC_APB1RSTR_BKPRST (1 << 27)
#define RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */
#define RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */
#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for CAN1RST */
#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for
CAN1RST */
#define RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */
#define RCC_APB1RSTR_I2C2RST (1 << 22)
#define RCC_APB1RSTR_I2C1RST (1 << 21)
@ -358,7 +362,8 @@ LGPL License Terms @ref lgpl_license
#define RCC_APB1ENR_BKPEN (1 << 27)
#define RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */
#define RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */
#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for CAN1EN */
#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for
CAN1EN */
#define RCC_APB1ENR_USBEN (1 << 23) /* (XX) */
#define RCC_APB1ENR_I2C2EN (1 << 22)
#define RCC_APB1ENR_I2C1EN (1 << 21)

3
include/libopencm3/stm32/f1/usb.h
View File

@ -6,7 +6,8 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Piotr Esden-Tempski <piotr@esden.net>
@author @htmlonly &copy; @endhtmlonly 2009
Piotr Esden-Tempski <piotr@esden.net>
@date 11 March 2013

3
include/libopencm3/stm32/f2/crc.h
View File

@ -1,6 +1,7 @@
/** @defgroup crc_defines CRC Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32F2xx CRC Generator </b>
@brief <b>libopencm3 Defined Constants and Types for the STM32F2xx CRC
Generator </b>
@ingroup STM32F2xx_defines

3
include/libopencm3/stm32/f2/iwdg.h
View File

@ -1,6 +1,7 @@
/** @defgroup iwdg_defines IWDG Defines
@brief <b>Defined Constants and Types for the STM32F2xx Independent Watchdog Timer</b>
@brief <b>Defined Constants and Types for the STM32F2xx Independent Watchdog
Timer</b>
@ingroup STM32F2xx_defines

2
include/libopencm3/stm32/f2/memorymap.h
View File

@ -22,7 +22,7 @@
#include <libopencm3/cm3/memorymap.h>
/* --- STM32F20x specific peripheral definitions ------------------------------- */
/* --- STM32F20x specific peripheral definitions --------------------------- */
/* Memory map for all busses */
#define PERIPH_BASE 0x40000000

2
include/libopencm3/stm32/f2/rcc.h
View File

@ -77,7 +77,7 @@
#define RCC_CR_HSIRDY (1 << 1)
#define RCC_CR_HSION (1 << 0)
/* --- RCC_PLLCFGR values ------------------------------------------------------- */
/* --- RCC_PLLCFGR values -------------------------------------------------- */
/* PLLQ: [27:24] */
#define RCC_PLLCFGR_PLLQ_SHIFT 24

36
include/libopencm3/stm32/f4/adc.h
View File

@ -1,13 +1,16 @@
/** @defgroup STM32F4xx_adc_defines ADC Defines
@brief <b>Defined Constants and Types for the STM32F4xx Analog to Digital Converters</b>
@brief <b>Defined Constants and Types for the STM32F4xx Analog to Digital
Converters</b>
@ingroup STM32F4xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Matthew Lai <m@matthewlai.ca>
@author @htmlonly &copy; @endhtmlonly 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
@author @htmlonly &copy; @endhtmlonly 2012
Matthew Lai <m@matthewlai.ca>
@author @htmlonly &copy; @endhtmlonly 2009
Edward Cheeseman <evbuilder@users.sourceforge.net>
@date 31 August 2012
@ -207,7 +210,7 @@ LGPL License Terms @ref lgpl_license
#define ADC_SR_EOC (1 << 1)
#define ADC_SR_AWD (1 << 0)
/* --- ADC_CR1 values specific to STM32F2,4------------------------------------ */
/* --- ADC_CR1 values specific to STM32F2,4--------------------------------- */
/* OVRIE: Overrun interrupt enable */
#define ADC_CR1_OVRIE (1 << 26)
@ -567,7 +570,8 @@ LGPL License Terms @ref lgpl_license
/* JL[2:0]: Discontinous mode channel count injected channels. */
/****************************************************************************/
/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro injected channels.
/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro
injected channels.
@ingroup STM32F4xx_adc_defines
@{*/
@ -733,10 +737,16 @@ LGPL License Terms @ref lgpl_license
/** All ADCs independent */
#define ADC_CCR_MULTI_INDEPENDENT (0x00 << 0)
/* dual modes (ADC1 + ADC2) */
/** Dual modes (ADC1 + ADC2) Combined regular simultaneous + injected simultaneous mode */
/* Dual modes (ADC1 + ADC2) */
/**
* Dual modes (ADC1 + ADC2) Combined regular simultaneous +
* injected simultaneous mode.
*/
#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_INJECTED_SIMUL (0x01 << 0)
/** Dual modes (ADC1 + ADC2) Combined regular simultaneous + alternate trigger mode. */
/**
* Dual modes (ADC1 + ADC2) Combined regular simultaneous +
* alternate trigger mode.
*/
#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG (0x02 << 0)
/** Dual modes (ADC1 + ADC2) Injected simultaneous mode only. */
#define ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0)
@ -748,9 +758,15 @@ LGPL License Terms @ref lgpl_license
#define ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0)
/* Triple modes (ADC1 + ADC2 + ADC3) */
/** Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + injected simultaneous mode */
/**
* Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous +
* injected simultaneous mode.
*/
#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0)
/** Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + alternate trigger mode. */
/**
* Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous +
* alternate trigger mode.
*/
#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0)
/** Triple modes (ADC1 + ADC2 + ADC3) Injected simultaneous mode only. */
#define ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0)

3
include/libopencm3/stm32/f4/crc.h
View File

@ -1,6 +1,7 @@
/** @defgroup crc_defines CRC Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32F4xx CRC Generator </b>
@brief <b>libopencm3 Defined Constants and Types for the STM32F4xx CRC
Generator </b>
@ingroup STM32F4xx_defines

3
include/libopencm3/stm32/f4/iwdg.h
View File

@ -1,6 +1,7 @@
/** @defgroup iwdg_defines IWDG Defines
@brief <b>Defined Constants and Types for the STM32F4xx Independent Watchdog Timer</b>
@brief <b>Defined Constants and Types for the STM32F4xx Independent Watchdog
Timer</b>
@ingroup STM32F4xx_defines

2
include/libopencm3/stm32/f4/rcc.h
View File

@ -78,7 +78,7 @@
#define RCC_CR_HSIRDY (1 << 1)
#define RCC_CR_HSION (1 << 0)
/* --- RCC_PLLCFGR values ------------------------------------------------------- */
/* --- RCC_PLLCFGR values -------------------------------------------------- */
/* PLLQ: [27:24] */
#define RCC_PLLCFGR_PLLQ_SHIFT 24

3
include/libopencm3/stm32/hash.h
View File

@ -22,5 +22,6 @@
#elif defined(STM32F4)
# include <libopencm3/stm32/f4/hash.h>
#else
# error "hash processor is supported only in stm32f21, stm32f41 and stm32f43 families."
# error "hash processor is supported only" \
"in stm32f21, stm32f41 and stm32f43 families."
#endif

3
include/libopencm3/stm32/l1/crc.h
View File

@ -1,6 +1,7 @@
/** @defgroup crc_defines CRC Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32L1xx CRC Generator </b>
@brief <b>libopencm3 Defined Constants and Types for the STM32L1xx CRC
Generator </b>
@ingroup STM32L1xx_defines

6
include/libopencm3/stm32/l1/dma.h
View File

@ -6,8 +6,10 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2011
Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
@date 18 October 2012

3
include/libopencm3/stm32/l1/flash.h
View File

@ -20,7 +20,8 @@
*/
/*
* All extracted from PM0062 rev2, L15xx and L16xx Flash/EEPROM programming manual
* All extracted from PM0062 rev2, L15xx and L16xx Flash/EEPROM programming
* manual.
*/
#ifndef LIBOPENCM3_FLASH_H

3
include/libopencm3/stm32/l1/iwdg.h
View File

@ -1,6 +1,7 @@
/** @defgroup iwdg_defines IWDG Defines
@brief <b>Defined Constants and Types for the STM32L1xx Independent Watchdog Timer</b>
@brief <b>Defined Constants and Types for the STM32L1xx Independent Watchdog
Timer</b>
@ingroup STM32L1xx_defines

9
include/libopencm3/stm32/l1/rcc.h
View File

@ -6,9 +6,12 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
@author @htmlonly &copy; @endhtmlonly 2009
Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
@author @htmlonly &copy; @endhtmlonly 2009
Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2012
Karl Palsson <karlp@tweak.net.au>
@date 11 November 2012

3
include/libopencm3/stm32/l1/timer.h
View File

@ -51,7 +51,8 @@ LGPL License Terms @ref lgpl_license
/* ITR1_RMP */
/****************************************************************************/
/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal Trigger 1 Remap
/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal
Trigger 1 Remap
@ingroup timer_defines
@{*/

27
include/libopencm3/stm32/otg_fs.h
View File

@ -39,7 +39,8 @@
#define OTG_FS_GCCFG MMIO32(USB_OTG_FS_BASE + 0x038)
#define OTG_FS_CID MMIO32(USB_OTG_FS_BASE + 0x03C)
#define OTG_FS_HPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x100)
#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 + 4*(x-1))
#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 + \
4*(x-1))
/* Host-mode Control and Status Registers */
#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400)
@ -66,22 +67,30 @@
#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C)
#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834)
#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900)
#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + 0x20*(x))
#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + \
0x20*(x))
#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00)
#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + 0x20*(x))
#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + 0x20*(x))
#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + 0x20*(x))
#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + \
0x20*(x))
#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + \
0x20*(x))
#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + \
0x20*(x))
#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910)
#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10)
#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + 0x20*(x))
#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + 0x20*(x))
#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x))
#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + \
0x20*(x))
#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + \
0x20*(x))
#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + \
0x20*(x))
/* Power and clock gating control and status register */
#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00)
/* Data FIFO */
#define OTG_FS_FIFO(x) ((volatile u32*)(USB_OTG_FS_BASE + (((x) + 1) << 12)))
#define OTG_FS_FIFO(x) ((volatile u32*)(USB_OTG_FS_BASE + \
(((x) + 1) << 12)))
/* Global CSRs */
/* OTG_FS USB control registers (OTG_HS_GOTGCTL) */

9
include/libopencm3/stm32/otg_hs.h
View File

@ -135,15 +135,18 @@
#define OTG_HS_DOEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPINT(x))
#define OTG_HS_DIEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ0)
#define OTG_HS_DOEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ0)
#define OTG_HS_DIEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ(x)))
#define OTG_HS_DIEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \
OTG_DIEPTSIZ(x))
#define OTG_HS_DTXFSTS(x) MMIO32(USB_OTG_HS_BASE + OTG_DTXFSTS(x))
#define OTG_HS_DOEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ(x))
#define OTG_HS_DOEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \
OTG_DOEPTSIZ(x))
/* Power and clock gating control and status register */
#define OTG_HS_PCGCCTL MMIO32(USB_OTG_HS_BASE + OTG_PCGCCTL)
/* Data FIFO */
#define OTG_HS_FIFO(x) ((volatile u32*)(USB_OTG_HS_BASE + OTG_FIFO(x)))
#define OTG_HS_FIFO(x) ((volatile u32*)(USB_OTG_HS_BASE + \
OTG_FIFO(x)))
/* Global CSRs */
/* OTG_HS USB control registers (OTG_FS_GOTGCTL) */

2
include/libopencm3/stm32/syscfg.h
View File

@ -22,7 +22,7 @@
#include <libopencm3/stm32/memorymap.h>
/* --- SYSCFG registers ------------------------------------------------------ */
/* --- SYSCFG registers ---------------------------------------------------- */
#define SYSCFG_MEMRM MMIO32(SYSCFG_BASE + 0x00)

2
include/libopencm3/stm32/tools.h
View File

@ -59,6 +59,6 @@ do { \
toggle_mask ^= bit_selector; \
} \
SET_REG(REG, toggle_mask); \
} while(0)
} while (0)
#endif

13
include/libopencm3/usb/cdc.h
View File

@ -6,7 +6,8 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Gareth McMullin <gareth@blacksphere.co.nz>
@author @htmlonly &copy; @endhtmlonly 2010
Gareth McMullin <gareth@blacksphere.co.nz>
@date 10 March 2013
@ -87,7 +88,7 @@ struct usb_cdc_union_descriptor {
u8 bControlInterface;
u8 bSubordinateInterface0;
/* ... */
} __attribute__((packed));
} __packed;
/* Definitions for Abstract Control Model devices from:
@ -102,7 +103,7 @@ struct usb_cdc_call_management_descriptor {
u8 bDescriptorSubtype;
u8 bmCapabilities;
u8 bDataInterface;
} __attribute__((packed));
} __packed;
/* Table 4: Abstract Control Management Functional Descriptor */
struct usb_cdc_acm_descriptor {
@ -110,7 +111,7 @@ struct usb_cdc_acm_descriptor {
u8 bDescriptorType;
u8 bDescriptorSubtype;
u8 bmCapabilities;
} __attribute__((packed));
} __packed;
/* Table 13: Class-Specific Request Codes for PSTN subclasses */
/* ... */
@ -125,7 +126,7 @@ struct usb_cdc_line_coding {
u8 bCharFormat;
u8 bParityType;
u8 bDataBits;
} __attribute__((packed));
} __packed;
/* Table 30: Class-Specific Notification Codes for PSTN subclasses */
/* ... */
@ -139,7 +140,7 @@ struct usb_cdc_notification {
u16 wValue;
u16 wIndex;
u16 wLength;
} __attribute__((packed));
} __packed;
#endif

5
include/libopencm3/usb/dfu.h
View File

@ -6,7 +6,8 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Gareth McMullin <gareth@blacksphere.co.nz>
@author @htmlonly &copy; @endhtmlonly 2010
Gareth McMullin <gareth@blacksphere.co.nz>
@date 10 March 2013
@ -93,7 +94,7 @@ struct usb_dfu_descriptor {
u16 wDetachTimeout;
u16 wTransferSize;
u16 bcdDFUVersion;
} __attribute__((packed));
} __packed;
#endif

5
include/libopencm3/usb/hid.h
View File

@ -6,7 +6,8 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Gareth McMullin <gareth@blacksphere.co.nz>
@author @htmlonly &copy; @endhtmlonly 2010
Gareth McMullin <gareth@blacksphere.co.nz>
@date 10 March 2013
@ -50,7 +51,7 @@ struct usb_hid_descriptor {
u16 bcdHID;
u8 bCountryCode;
u8 bNumDescriptors;
} __attribute__((packed));
} __packed;
#endif

5
include/libopencm3/usb/usbd.h
View File

@ -6,7 +6,8 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Gareth McMullin <gareth@blacksphere.co.nz>
@author @htmlonly &copy; @endhtmlonly 2010
Gareth McMullin <gareth@blacksphere.co.nz>
@date 10 March 2013
@ -58,7 +59,7 @@ extern const usbd_driver stm32f207_usb_driver;
#define otghs_usb_driver stm32f207_usb_driver
/* <usb.c> */
extern usbd_device *usbd_init(const usbd_driver *driver,
extern usbd_device * usbd_init(const usbd_driver *driver,
const struct usb_device_descriptor *dev,
const struct usb_config_descriptor *conf,
const char **strings, int num_strings,

22
include/libopencm3/usb/usbstd.h
View File

@ -1,12 +1,14 @@
/** @defgroup usb_type_defines USB Standard Structure Definitions
@brief <b>Defined Constants and Types for the USB Standard Structure Definitions</b>
@brief <b>Defined Constants and Types for the USB Standard Structure
Definitions</b>
@ingroup USB_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Gareth McMullin <gareth@blacksphere.co.nz>
@author @htmlonly &copy; @endhtmlonly 2010
Gareth McMullin <gareth@blacksphere.co.nz>
@date 10 March 2013
@ -57,7 +59,7 @@ struct usb_setup_data {
u16 wValue;
u16 wIndex;
u16 wLength;
} __attribute__((packed));
} __packed;
/* Class Definition */
#define USB_CLASS_VENDOR 0xFF
@ -129,7 +131,7 @@ struct usb_device_descriptor {
u8 iProduct;
u8 iSerialNumber;
u8 bNumConfigurations;
} __attribute__((packed));
} __packed;
#define USB_DT_DEVICE_SIZE sizeof(struct usb_device_descriptor)
@ -146,7 +148,7 @@ struct usb_device_qualifier_descriptor {
u8 bMaxPacketSize0;
u8 bNumConfigurations;
u8 bReserved;
} __attribute__((packed));
} __packed;
/* USB Standard Configuration Descriptor - Table 9-10 */
struct usb_config_descriptor {
@ -165,7 +167,7 @@ struct usb_config_descriptor {
const struct usb_iface_assoc_descriptor *iface_assoc;
const struct usb_interface_descriptor *altsetting;
} *interface;
} __attribute__((packed));
} __packed;
#define USB_DT_CONFIGURATION_SIZE 9
/* USB Configuration Descriptor bmAttributes bit definitions */
@ -192,7 +194,7 @@ struct usb_interface_descriptor {
const struct usb_endpoint_descriptor *endpoint;
const void *extra;
int extralen;
} __attribute__((packed));
} __packed;
#define USB_DT_INTERFACE_SIZE 9
/* USB Standard Endpoint Descriptor - Table 9-13 */
@ -203,7 +205,7 @@ struct usb_endpoint_descriptor {
u8 bmAttributes;
u16 wMaxPacketSize;
u8 bInterval;
} __attribute__((packed));
} __packed;
#define USB_DT_ENDPOINT_SIZE sizeof(struct usb_endpoint_descriptor)
/* USB Endpoint Descriptor bmAttributes bit definitions */
@ -228,7 +230,7 @@ struct usb_string_descriptor {
u8 bLength;
u8 bDescriptorType;
u16 wData[];
} __attribute__((packed));
} __packed;
/* From ECN: Interface Association Descriptors, Table 9-Z */
struct usb_iface_assoc_descriptor {
@ -240,7 +242,7 @@ struct usb_iface_assoc_descriptor {
u8 bFunctionSubClass;
u8 bFunctionProtocol;
u8 iFunction;
} __attribute__((packed));
} __packed;
#define USB_DT_INTERFACE_ASSOCIATION_SIZE \
sizeof(struct usb_iface_assoc_descriptor)

26
include/libopencmsis/core_cm3.h
View File

@ -4,7 +4,8 @@
* particularly unimplemented features are FIXME'd extra
* */
/* the original core_cm3.h is nonfree by arm; this provides libopencm3 variant of the symbols efm32lib needs of CMSIS. */
/* the original core_cm3.h is nonfree by arm; this provides libopencm3 variant
* of the symbols efm32lib needs of CMSIS. */
#ifndef OPENCMSIS_CORECM3_H
#define OPENCMSIS_CORECM3_H
@ -35,8 +36,7 @@
/* structure as in, for example,
* DeviceSupport/EnergyMicro/EFM32/efm32tg840f32.h, data from
* libopencm3/cm3/scb.h. FIXME incomplete. */
typedef struct
{
typedef struct {
__IO uint32_t CPUID;
__IO uint32_t ICSR;
__IO uint32_t VTOR;
@ -55,12 +55,13 @@ typedef struct
/* needed by efm32_cmu.h, probably it's just what gcc provides anyway */
#define __CLZ(div) __builtin_clz(div)
/* needed by efm32_aes.c. __builtin_bswap32 does the same thing as the rev instruction according to https://bugzilla.mozilla.org/show_bug.cgi?id=600106 */
/* needed by efm32_aes.c. __builtin_bswap32 does the same thing as the rev
* instruction according to https://bugzilla.mozilla.org/show_bug.cgi?id=600106
*/
#define __REV(x) __builtin_bswap32(x)
/* stubs for efm32_dbg.h */
typedef struct
{
typedef struct {
uint32_t DHCSR;
uint32_t DEMCR; /* needed by efm32tg stk trace.c */
} CoreDebug_TypeDef;
@ -94,8 +95,7 @@ static inline void NVIC_DisableIRQ(uint8_t irqn)
#define SCB_SHCSR_MEMFAULTENA_Msk 0
typedef struct
{
typedef struct {
uint32_t CTRL;
uint32_t RNR;
uint32_t RBAR;
@ -133,8 +133,7 @@ typedef struct
* */
/* from d0002_efm32_cortex-m3_reference_manual.pdf section 4.4 */
typedef struct
{
typedef struct {
uint32_t CTRL;
uint32_t LOAD;
uint32_t VAL;
@ -146,7 +145,9 @@ static inline uint32_t SysTick_Config(uint32_t n_ticks)
{
/* constant from systick_set_reload -- as this returns something that's
* not void, this is the only possible error condition */
if (n_ticks & ~0x00FFFFFF) return 1;
if (n_ticks & ~0x00FFFFFF) {
return 1;
}
systick_set_reload(n_ticks);
systick_set_clocksource(true);
@ -157,8 +158,7 @@ static inline uint32_t SysTick_Config(uint32_t n_ticks)
}
/* stubs for efm32tg stk trace.c */
typedef struct
{
typedef struct {
uint32_t LAR;
uint32_t TCR;
} ITM_TypeDef;

2
lib/cm3/assert.c
View File

@ -21,7 +21,7 @@
void __attribute__((weak)) cm3_assert_failed(void)
{
while(1);
while (1);
}
void __attribute__((weak)) cm3_assert_failed_verbose(

39
lib/cm3/nvic.c
View File

@ -45,7 +45,7 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/cm3/nvic.h>
#include <libopencm3/cm3/scs.h>
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief NVIC Enable Interrupt
Enables a user interrupt.
@ -58,7 +58,7 @@ void nvic_enable_irq(u8 irqn)
NVIC_ISER(irqn / 32) = (1 << (irqn % 32));
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief NVIC Disable Interrupt
Disables a user interrupt.
@ -71,7 +71,7 @@ void nvic_disable_irq(u8 irqn)
NVIC_ICER(irqn / 32) = (1 << (irqn % 32));
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief NVIC Return Pending Interrupt
True if the interrupt has occurred and is waiting for service.
@ -85,7 +85,7 @@ u8 nvic_get_pending_irq(u8 irqn)
return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief NVIC Set Pending Interrupt
Force a user interrupt to a pending state. This has no effect if the interrupt
@ -99,7 +99,7 @@ void nvic_set_pending_irq(u8 irqn)
NVIC_ISPR(irqn / 32) = (1 << (irqn % 32));
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief NVIC Clear Pending Interrupt
Force remove a user interrupt from a pending state. This has no effect if the
@ -113,7 +113,7 @@ void nvic_clear_pending_irq(u8 irqn)
NVIC_ICPR(irqn / 32) = (1 << (irqn % 32));
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief NVIC Return Active Interrupt
Interrupt has occurred and is currently being serviced.
@ -127,7 +127,7 @@ u8 nvic_get_active_irq(u8 irqn)
return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief NVIC Return Enabled Interrupt
@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
@ -139,13 +139,14 @@ u8 nvic_get_irq_enabled(u8 irqn)
return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief NVIC Set Interrupt Priority
There are 16 priority levels only, given by the upper four bits of the priority
byte, as required by ARM standards. The priority levels are interpreted according
to the pre-emptive priority grouping set in the SCB Application Interrupt and Reset
Control Register (SCB_AIRCR), as done in @ref scb_set_priority_grouping.
byte, as required by ARM standards. The priority levels are interpreted
according to the pre-emptive priority grouping set in the SCB Application
Interrupt and Reset Control Register (SCB_AIRCR), as done in @ref
scb_set_priority_grouping.
@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
@param[in] priority Unsigned int8. Interrupt priority (0 ... 255 in steps of 16)
@ -156,29 +157,29 @@ void nvic_set_priority(u8 irqn, u8 priority)
/* code from lpc43xx/nvic.c -- this is quite a hack and alludes to the
* negative interrupt numbers assigned to the system interrupts. better
* handling would mean signed integers. */
if(irqn>=NVIC_IRQ_COUNT)
{
if (irqn >= NVIC_IRQ_COUNT) {
/* Cortex-M system interrupts */
SCS_SHPR( (irqn&0xF)-4 ) = priority;
}else
{
SCS_SHPR((irqn & 0xF) - 4) = priority;
} else {
/* Device specific interrupts */
NVIC_IPR(irqn) = priority;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief NVIC Software Trigger Interrupt
Generate an interrupt from software. This has no effect for unprivileged access
unless the privilege level has been elevated through the System Control Registers.
unless the privilege level has been elevated through the System Control
Registers.
@param[in] irqn Unsigned int16. Interrupt number (0 ... 239)
*/
void nvic_generate_software_interrupt(u16 irqn)
{
if (irqn <= 239)
if (irqn <= 239) {
NVIC_STIR |= irqn;
}
}
/**@}*/

4
lib/cm3/scb.c
View File

@ -25,14 +25,14 @@ void scb_reset_core(void)
{
SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET;
while(1);
while (1);
}
void scb_reset_system(void)
{
SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ;
while(1);
while (1);
}
void scb_set_priority_grouping(u32 prigroup)

12
lib/cm3/sync.c
View File

@ -19,18 +19,18 @@
#include <libopencm3/cm3/sync.h>
u32 __ldrex(volatile u32* addr)
u32 __ldrex(volatile u32 *addr)
{
u32 res;
__asm__ volatile ("ldrex %0, [%1]" : "=r" (res) : "r" (addr));
return res;
}
u32 __strex(u32 val, volatile u32* addr)
u32 __strex(u32 val, volatile u32 *addr)
{
u32 res;
__asm__ volatile ("strex %0, %2, [%1]" :
"=&r" (res) : "r" (addr), "r" (val));
__asm__ volatile ("strex %0, %2, [%1]"
: "=&r" (res) : "r" (addr), "r" (val));
return res;
}
@ -39,7 +39,7 @@ void __dmb()
__asm__ volatile ("dmb");
}
void mutex_lock(mutex_t* m)
void mutex_lock(mutex_t *m)
{
u32 status = 0;
@ -57,7 +57,7 @@ void mutex_lock(mutex_t* m)
__dmb();
}
void mutex_unlock(mutex_t* m)
void mutex_unlock(mutex_t *m)
{
__dmb();

38
lib/cm3/systick.c
View File

@ -40,7 +40,7 @@ LGPL License Terms @ref lgpl_license
/**@{*/
#include <libopencm3/cm3/systick.h>
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SysTick Set the Automatic Reload Value.
The counter is set to the reload value when the counter starts and after it
@ -54,7 +54,7 @@ void systick_set_reload(u32 value)
STK_LOAD = (value & 0x00FFFFFF);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SysTick Read the Automatic Reload Value.
@returns 24 bit reload value as u32.
@ -62,10 +62,10 @@ void systick_set_reload(u32 value)
u32 systick_get_reload(void)
{
return (STK_LOAD & 0x00FFFFFF);
return STK_LOAD & 0x00FFFFFF;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Get the current SysTick counter value.
@returns 24 bit current value as u32.
@ -73,10 +73,10 @@ u32 systick_get_reload(void)
u32 systick_get_value(void)
{
return (STK_VAL & 0x00FFFFFF);
return STK_VAL & 0x00FFFFFF;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Set the SysTick Clock Source.
The clock source can be either the AHB clock or the same clock divided by 8.
@ -86,11 +86,12 @@ The clock source can be either the AHB clock or the same clock divided by 8.
void systick_set_clocksource(u8 clocksource)
{
if (clocksource < 2)
if (clocksource < 2) {
STK_CTRL |= (clocksource << STK_CTRL_CLKSOURCE_LSB);
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Enable SysTick Interrupt.
*/
@ -100,7 +101,7 @@ void systick_interrupt_enable(void)
STK_CTRL |= STK_CTRL_TICKINT;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Disable SysTick Interrupt.
*/
@ -110,7 +111,7 @@ void systick_interrupt_disable(void)
STK_CTRL &= ~STK_CTRL_TICKINT;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Enable SysTick Counter.
*/
@ -120,7 +121,7 @@ void systick_counter_enable(void)
STK_CTRL |= STK_CTRL_ENABLE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Disable SysTick Counter.
*/
@ -130,31 +131,32 @@ void systick_counter_disable(void)
STK_CTRL &= ~STK_CTRL_ENABLE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SysTick Read the Counter Flag.
The count flag is set when the timer count becomes zero, and is cleared when the
flag is read.
The count flag is set when the timer count becomes zero, and is cleared when
the flag is read.
@returns Boolean if flag set.
*/
u8 systick_get_countflag(void)
{
if (STK_CTRL & STK_CTRL_COUNTFLAG)
if (STK_CTRL & STK_CTRL_COUNTFLAG) {
return 1;
else
} else {
return 0;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief SysTick Get Calibration Value
@returns Current calibration value
*/
u32 systick_get_calib(void)
{
return (STK_CALIB&0x00FFFFFF);
return STK_CALIB & 0x00FFFFFF;
}
/**@}*/

22
lib/cm3/vector.c
View File

@ -25,8 +25,6 @@
/* load the weak symbols for IRQ_HANDLERS */
#include "../dispatch/vector_nvic.c"
#define WEAK __attribute__ ((weak))
/* Symbols exported by the linker script(s): */
extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
typedef void (*funcp_t) (void);
@ -61,17 +59,23 @@ void WEAK __attribute__ ((naked)) reset_handler(void)
volatile unsigned *src, *dest;
funcp_t *fp;
for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++)
for (src = &_data_loadaddr, dest = &_data;
dest < &_edata;
src++, dest++) {
*dest = *src;
}
while (dest < &_ebss)
while (dest < &_ebss) {
*dest++ = 0;
}
/* Constructors. */
for (fp = &__preinit_array_start; fp < &__preinit_array_end; fp++)
for (fp = &__preinit_array_start; fp < &__preinit_array_end; fp++) {
(*fp)();
for (fp = &__init_array_start; fp < &__init_array_end; fp++)
}
for (fp = &__init_array_start; fp < &__init_array_end; fp++) {
(*fp)();
}
/* might be provided by platform specific vector.c */
pre_main();
@ -80,13 +84,15 @@ void WEAK __attribute__ ((naked)) reset_handler(void)
main();
/* Destructors. */
for (fp = &__fini_array_start; fp < &__fini_array_end; fp++)
for (fp = &__fini_array_start; fp < &__fini_array_end; fp++) {
(*fp)();
}
}
void blocking_handler(void)
{
while (1) ;
while (1);
}
void null_handler(void)

3
lib/dispatch/vector_nvic.c
View File

@ -33,7 +33,8 @@
# include "../lm3s/vector_nvic.c"
#else
# warning"no interrupts defined for chipset; not allocating space in the vector table"
# warning "no interrupts defined for chipset;"\
"not allocating space in the vector table"
#define IRQ_HANDLERS

3
lib/lm3s/gpio.c
View File

@ -6,7 +6,8 @@
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2011 Gareth McMullin <gareth@blacksphere.co.nz>
@author @htmlonly &copy; @endhtmlonly 2011
Gareth McMullin <gareth@blacksphere.co.nz>
@date 10 March 2013

19
lib/lm4f/gpio.c
View File

@ -25,8 +25,10 @@
*
* @version 1.0.0
*
* @author @htmlonly &copy; @endhtmlonly 2011 Gareth McMullin <gareth@blacksphere.co.nz>
* @author @htmlonly &copy; @endhtmlonly 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
* @author @htmlonly &copy; @endhtmlonly 2011
* Gareth McMullin <gareth@blacksphere.co.nz>
* @author @htmlonly &copy; @endhtmlonly 2013
* Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* @date 16 March 2013
*
@ -268,17 +270,17 @@ void gpio_mode_setup(u32 gpioport, enum gpio_mode mode, enum gpio_pullup pullup,
void gpio_set_output_config(u32 gpioport, enum gpio_output_type otype,
enum gpio_drive_strength drive, u8 gpios)
{
if (otype == GPIO_OTYPE_OD)
if (otype == GPIO_OTYPE_OD) {
GPIO_ODR(gpioport) |= gpios;
else
} else {
GPIO_ODR(gpioport) &= ~gpios;
}
/*
* Setting a bit in the GPIO_DRxR register clears the corresponding bit
* in the other GPIO_DRyR registers, and vice-versa.
*/
switch (drive)
{
switch (drive) {
case GPIO_DRIVE_8MA_SLEW_CTL:
GPIO_DR8R(gpioport) |= gpios;
GPIO_SLR(gpioport) |= gpios;
@ -338,11 +340,12 @@ void gpio_set_af(u32 gpioport, u8 alt_func_num, u8 gpios)
for (i = 0; i < 8; i++) {
pin_mask = (1 << i);
if (!(gpios & pin_mask))
if (!(gpios & pin_mask)) {
continue;
}
pctl32 &= ~PCTL_MASK(i);
pctl32 |= PCTL_AF( i, (alt_func_num & 0xf) );
pctl32 |= PCTL_AF(i, (alt_func_num & 0xf));
}
GPIO_PCTL(gpioport) = pctl32;

8
lib/lm4f/rcc.c
View File

@ -23,7 +23,8 @@
*
* @ingroup LM4Fxx
*
@author @htmlonly &copy; @endhtmlonly 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012
Alexandru Gagniuc <mr.nuke.me@gmail.com>
* \brief <b>libopencm3 LM4F Clock control API</b>
*
@ -334,7 +335,7 @@ void rcc_usb_pll_on(void)
*/
void rcc_wait_for_pll_ready(void)
{
while(!(SYSCTL_PLLSTAT & SYSCTL_PLLSTAT_LOCK));
while (!(SYSCTL_PLLSTAT & SYSCTL_PLLSTAT_LOCK));
}
/**
@ -448,8 +449,9 @@ void rcc_sysclk_config(osc_src_t osc_src, xtal_t xtal, u8 pll_div400)
rcc_pll_bypass_enable();
/* Enable the main oscillator, if needed */
if (osc_src == OSCSRC_MOSC)
if (osc_src == OSCSRC_MOSC) {
rcc_enable_main_osc();
}
/* Make RCC2 override RCC */
rcc_enable_rcc2();

28
lib/lm4f/uart.c
View File

@ -116,10 +116,11 @@ void uart_set_baudrate(u32 uart, u32 baud)
u32 clock;
/* Are we running off the internal clock or system clock? */
if (UART_CC(uart) == UART_CC_CS_PIOSC)
if (UART_CC(uart) == UART_CC_CS_PIOSC) {
clock = 16000000;
else
} else {
clock = rcc_get_system_clock_frequency();
}
/* Find the baudrate divisor */
u32 div = (((clock * 8) / baud) + 1) / 2;
@ -158,10 +159,11 @@ void uart_set_databits(u32 uart, u8 databits)
*/
void uart_set_stopbits(u32 uart, u8 stopbits)
{
if (stopbits == 2)
if (stopbits == 2) {
UART_LCRH(uart) |= UART_LCRH_STP2;
else
} else {
UART_LCRH(uart) &= ~UART_LCRH_STP2;
}
}
/**
@ -178,8 +180,7 @@ void uart_set_parity(u32 uart, enum uart_parity parity)
reg32 |= UART_LCRH_PEN;
reg32 &= ~(UART_LCRH_SPS | UART_LCRH_EPS);
switch (parity)
{
switch (parity) {
case UART_PARITY_NONE:
/* Once we disable parity the other bits are meaningless */
UART_LCRH(uart) &= ~UART_LCRH_PEN;
@ -218,12 +219,13 @@ void uart_set_flow_control(u32 uart, enum uart_flowctl flow)
reg32 &= ~(UART_CTL_RTSEN | UART_CTL_CTSEN);
if (flow == UART_FLOWCTL_RTS)
if (flow == UART_FLOWCTL_RTS) {
reg32 |= UART_CTL_RTSEN;
else if (flow == UART_FLOWCTL_CTS)
} else if (flow == UART_FLOWCTL_CTS) {
reg32 |= UART_CTL_CTSEN;
else if (flow == UART_FLOWCTL_RTS_CTS)
} else if (flow == UART_FLOWCTL_RTS_CTS) {
reg32 |= (UART_CTL_RTSEN | UART_CTL_CTSEN);
}
UART_CTL(uart) = reg32;
}
@ -301,7 +303,7 @@ u16 uart_recv(u32 uart)
void uart_wait_send_ready(u32 uart)
{
/* Wait until the Tx FIFO is no longer full */
while(UART_FR(uart) & UART_FR_TXFF);
while (UART_FR(uart) & UART_FR_TXFF);
}
/**
@ -314,7 +316,7 @@ void uart_wait_send_ready(u32 uart)
void uart_wait_recv_ready(u32 uart)
{
/* Wait until the Tx FIFO is no longer empty */
while(UART_FR(uart) & UART_FR_RXFE);
while (UART_FR(uart) & UART_FR_RXFE);
}
/**
@ -438,8 +440,8 @@ void uart_enable_interrupts(u32 uart, enum uart_interrupt_flag ints)
* interrupts, pass (UART_INT_RX | UART_INT_CTS)
*
* @param[in] uart UART block register address base @ref uart_reg_base
* @param[in] ints Interrupts which to disable. Any combination of interrupts may
* be specified by OR'ing then together
* @param[in] ints Interrupts which to disable. Any combination of interrupts
* may be specified by OR'ing then together
*/
void uart_disable_interrupts(u32 uart, enum uart_interrupt_flag ints)
{

113
lib/lm4f/usb_lm4f.c
View File

@ -232,8 +232,9 @@ static void lm4f_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size,
if (addr == 0) {
USB_EPIDX = 0;
if (reg8 > USB_FIFOSZ_SIZE_64)
if (reg8 > USB_FIFOSZ_SIZE_64) {
reg8 = USB_FIFOSZ_SIZE_64;
}
/* The RX and TX FIFOs are shared for EP0 */
USB_RXFIFOSZ = reg8;
@ -248,8 +249,9 @@ static void lm4f_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size,
}
/* Are we out of FIFO space? */
if (usbd_dev->fifo_mem_top + fifo_size > MAX_FIFO_RAM)
if (usbd_dev->fifo_mem_top + fifo_size > MAX_FIFO_RAM) {
return;
}
USB_EPIDX = addr & USB_EPIDX_MASK;
@ -262,12 +264,12 @@ static void lm4f_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size,
usbd_dev->user_callback_ctr[ep][USB_TRANSACTION_IN] =
(void *)callback;
}
if (type == USB_ENDPOINT_ATTR_ISOCHRONOUS)
if (type == USB_ENDPOINT_ATTR_ISOCHRONOUS) {
USB_TXCSRH(ep) |= USB_TXCSRH_ISO;
else
} else {
USB_TXCSRH(ep) &= ~USB_TXCSRH_ISO;
}
else {
} else {
USB_RXMAXP(ep) = max_size;
USB_RXFIFOSZ = reg8;
USB_RXFIFOADD = ((usbd_dev->fifo_mem_top) >> 3);
@ -275,11 +277,12 @@ static void lm4f_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size,
usbd_dev->user_callback_ctr[ep][USB_TRANSACTION_OUT] =
(void *)callback;
}
if (type == USB_ENDPOINT_ATTR_ISOCHRONOUS)
if (type == USB_ENDPOINT_ATTR_ISOCHRONOUS) {
USB_RXCSRH(ep) |= USB_RXCSRH_ISO;
else
} else {
USB_RXCSRH(ep) &= ~USB_RXCSRH_ISO;
}
}
usbd_dev->fifo_mem_top += fifo_size;
}
@ -301,25 +304,28 @@ static void lm4f_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall)
const bool dir_tx = addr & 0x80;
if (ep == 0) {
if (stall)
if (stall) {
USB_CSRL0 |= USB_CSRL0_STALL;
else
} else {
USB_CSRL0 &= ~USB_CSRL0_STALL;
}
return;
}
if (dir_tx) {
if (stall)
if (stall) {
(USB_TXCSRL(ep)) |= USB_TXCSRL_STALL;
else
} else {
(USB_TXCSRL(ep)) &= ~USB_TXCSRL_STALL;
}
}
else {
if (stall)
if (stall) {
(USB_RXCSRL(ep)) |= USB_RXCSRL_STALL;
else
} else {
(USB_RXCSRL(ep)) &= ~USB_RXCSRL_STALL;
}
}
}
static u8 lm4f_ep_stall_get(usbd_device *usbd_dev, u8 addr)
@ -330,13 +336,14 @@ static u8 lm4f_ep_stall_get(usbd_device *usbd_dev, u8 addr)
const bool dir_tx = addr & 0x80;
if (ep == 0) {
return (USB_CSRL0 & USB_CSRL0_STALLED);
return USB_CSRL0 & USB_CSRL0_STALLED;
}
if (dir_tx)
return (USB_TXCSRL(ep) & USB_TXCSRL_STALLED);
else
return (USB_RXCSRL(ep) & USB_RXCSRL_STALLED);
if (dir_tx) {
return USB_TXCSRL(ep) & USB_TXCSRL_STALLED;
} else {
return USB_RXCSRL(ep) & USB_RXCSRL_STALLED;
}
}
static void lm4f_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak)
@ -368,14 +375,16 @@ static u16 lm4f_ep_write_packet(usbd_device *usbd_dev, u8 addr,
* the reads are downgraded to 8-bit in hardware. We lose a bit of
* performance, but we don't crash.
*/
for (i = 0; i < (len & ~0x3); i += 4)
for (i = 0; i < (len & ~0x3); i += 4) {
USB_FIFO32(ep) = *((u32 *)(buf + i));
}
if (len & 0x2) {
USB_FIFO16(ep) = *((u16 *)(buf + i));
i += 2;
}
if (len & 0x1)
if (len & 0x1) {
USB_FIFO8(ep) = *((u8 *)(buf + i));
}
if (ep == 0) {
/*
@ -384,11 +393,11 @@ static u16 lm4f_ep_write_packet(usbd_device *usbd_dev, u8 addr,
* that is a multiple of 64 bytes will end with a zero-length
* packet, so our check is sane.
*/
if (len != 64)
if (len != 64) {
USB_CSRL0 |= USB_CSRL0_TXRDY | USB_CSRL0_DATAEND;
else
} else {
USB_CSRL0 |= USB_CSRL0_TXRDY;
}
} else {
USB_TXCSRL(ep) |= USB_TXCSRL_TXRDY;
}
@ -396,7 +405,8 @@ static u16 lm4f_ep_write_packet(usbd_device *usbd_dev, u8 addr,
return i;
}
static u16 lm4f_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf, u16 len)
static u16 lm4f_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf,
u16 len)
{
(void)usbd_dev;
@ -412,14 +422,16 @@ static u16 lm4f_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf, u16 le
* the writes are downgraded to 8-bit in hardware. We lose a bit of
* performance, but we don't crash.
*/
for (len = 0; len < (rlen & ~0x3); len += 4)
for (len = 0; len < (rlen & ~0x3); len += 4) {
*((u32 *)(buf + len)) = USB_FIFO32(ep);
}
if (rlen & 0x2) {
*((u16 *)(buf + len)) = USB_FIFO16(ep);
len += 2;
}
if (rlen & 0x1)
if (rlen & 0x1) {
*((u8 *)(buf + len)) = USB_FIFO8(ep);
}
if (ep == 0) {
/*
@ -456,17 +468,21 @@ static void lm4f_poll(usbd_device *usbd_dev)
const u8 usb_txis = USB_TXIS;
const u8 usb_csrl0 = USB_CSRL0;
if ((usb_is & USB_IM_SUSPEND) && (usbd_dev->user_callback_suspend))
if ((usb_is & USB_IM_SUSPEND) && (usbd_dev->user_callback_suspend)) {
usbd_dev->user_callback_suspend();
}
if ((usb_is & USB_IM_RESUME) && (usbd_dev->user_callback_resume))
if ((usb_is & USB_IM_RESUME) && (usbd_dev->user_callback_resume)) {
usbd_dev->user_callback_resume();
}
if (usb_is & USB_IM_RESET)
if (usb_is & USB_IM_RESET) {
_usbd_reset(usbd_dev);
}
if ((usb_is & USB_IM_SOF) && (usbd_dev->user_callback_sof))
if ((usb_is & USB_IM_SOF) && (usbd_dev->user_callback_sof)) {
usbd_dev->user_callback_sof();
}
if (usb_txis & USB_EP0) {
/*
@ -483,14 +499,17 @@ static void lm4f_poll(usbd_device *usbd_dev)
type = (usbd_dev->control_state.state != DATA_OUT &&
usbd_dev->control_state.state != LAST_DATA_OUT)
? USB_TRANSACTION_SETUP :
USB_TRANSACTION_OUT ;
USB_TRANSACTION_OUT;
if (usbd_dev->user_callback_ctr[0][type])
usbd_dev->user_callback_ctr[0][type] (usbd_dev, 0);
if (usbd_dev->user_callback_ctr[0][type]) {
usbd_dev->
user_callback_ctr[0][type](usbd_dev, 0);
}
} else {
tx_cb = usbd_dev->user_callback_ctr[0][USB_TRANSACTION_IN];
tx_cb = usbd_dev->user_callback_ctr[0]
[USB_TRANSACTION_IN];
/*
* EP0 bit in TXIS is set not only when a packet is
@ -508,11 +527,13 @@ static void lm4f_poll(usbd_device *usbd_dev)
*/
if ((usbd_dev->control_state.state != DATA_IN) &&
(usbd_dev->control_state.state != LAST_DATA_IN) &&
(usbd_dev->control_state.state != STATUS_IN))
(usbd_dev->control_state.state != STATUS_IN)) {
return;
}
if (tx_cb)
tx_cb (usbd_dev, 0);
if (tx_cb) {
tx_cb(usbd_dev, 0);
}
}
}
@ -521,12 +542,14 @@ static void lm4f_poll(usbd_device *usbd_dev)
tx_cb = usbd_dev->user_callback_ctr[i][USB_TRANSACTION_IN];
rx_cb = usbd_dev->user_callback_ctr[i][USB_TRANSACTION_OUT];
if ( (usb_txis & (1 << i)) && tx_cb)
if ((usb_txis & (1 << i)) && tx_cb) {
tx_cb(usbd_dev, i);
}
if ( (usb_rxis & (1 << i)) && rx_cb)
if ((usb_rxis & (1 << i)) && rx_cb) {
rx_cb(usbd_dev, i);
}
}
}
@ -540,10 +563,11 @@ static void lm4f_disconnect(usbd_device *usbd_dev, bool disconnected)
* usbd_disconnect(dev, 1) followed by usbd_disconnect(dev, 0)
* causes the device to re-enumerate and re-configure properly.
*/
if (disconnected)
if (disconnected) {
lm4f_usb_soft_disconnect();
else
} else {
lm4f_usb_soft_connect();
}
}
/*
@ -568,8 +592,9 @@ static usbd_device *lm4f_usbd_init(void)
/* Software reset USB */
SYSCTL_SRUSB = 1;
for (i = 0; i < 1000; i++)
for (i = 0; i < 1000; i++) {
__asm__("nop");
}
SYSCTL_SRUSB = 0;
/*
@ -579,8 +604,8 @@ static usbd_device *lm4f_usbd_init(void)
*/
/* Wait for it */
i = 0;
while ( (SYSCTL_RIS & SYSCTL_RIS_USBPLLLRIS) == 0) {
i ++;
while ((SYSCTL_RIS & SYSCTL_RIS_USBPLLLRIS) == 0) {
i++;
if (i > 0xffff) {
return 0;
}

9
lib/lpc43xx/i2c.c
View File

@ -81,8 +81,9 @@ void i2c0_tx_start(void)
/* transmit data byte */
void i2c0_tx_byte(u8 byte)
{
if (I2C0_CONSET & I2C_CONSET_STA)
if (I2C0_CONSET & I2C_CONSET_STA) {
I2C0_CONCLR = I2C_CONCLR_STAC;
}
I2C0_DAT = byte;
I2C0_CONCLR = I2C_CONCLR_SIC;
while (!(I2C0_CONSET & I2C_CONSET_SI));
@ -91,8 +92,9 @@ void i2c0_tx_byte(u8 byte)
/* receive data byte */
u8 i2c0_rx_byte(void)
{
if (I2C0_CONSET & I2C_CONSET_STA)
if (I2C0_CONSET & I2C_CONSET_STA) {
I2C0_CONCLR = I2C_CONCLR_STAC;
}
I2C0_CONCLR = I2C_CONCLR_SIC;
while (!(I2C0_CONSET & I2C_CONSET_SI));
return I2C0_DAT;
@ -101,8 +103,9 @@ u8 i2c0_rx_byte(void)
/* transmit stop bit */
void i2c0_stop(void)
{
if (I2C0_CONSET & I2C_CONSET_STA)
if (I2C0_CONSET & I2C_CONSET_STA) {
I2C0_CONCLR = I2C_CONCLR_STAC;
}
I2C0_CONSET = I2C_CONSET_STO;
I2C0_CONCLR = I2C_CONCLR_SIC;
}

8
lib/lpc43xx/scu.c
View File

@ -34,13 +34,17 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/lpc43xx/scu.h>
/* For pin_conf_normal value see scu.h define SCU_CONF_XXX or Configuration for different I/O pins types */
/* For pin_conf_normal value see scu.h define SCU_CONF_XXX or Configuration for
* different I/O pins types
*/
void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf)
{
MMIO32(group_pin) = scu_conf;
}
/* For other special SCU register USB1, I2C0, ADC0/1, DAC, EMC clock delay See scu.h */
/* For other special SCU register USB1, I2C0, ADC0/1, DAC, EMC clock delay See
* scu.h
*/
/* For Pin interrupt select register see scu.h SCU_PINTSEL0 & SCU_PINTSEL1 */

43
lib/lpc43xx/ssp.c
View File

@ -61,11 +61,9 @@ void ssp_disable(ssp_num_t ssp_num)
{
u32 ssp_port;
if(ssp_num == SSP0_NUM)
{
if (ssp_num == SSP0_NUM) {
ssp_port = SSP0;
}else
{
} else {
ssp_port = SSP1;
}
/* Disable SSP */
@ -88,16 +86,15 @@ void ssp_init(ssp_num_t ssp_num,
u32 ssp_port;
u32 clock;
if(ssp_num == SSP0_NUM)
{
if (ssp_num == SSP0_NUM) {
ssp_port = SSP0;
}else
{
} else {
ssp_port = SSP1;
}
/* use PLL1 as clock source for SSP1 */
CGU_BASE_SSP1_CLK = (CGU_SRC_PLL1<<CGU_BASE_CLK_SEL_SHIFT) | (1<<CGU_AUTOBLOCK_CLOCK_BIT);
CGU_BASE_SSP1_CLK = (CGU_SRC_PLL1<<CGU_BASE_CLK_SEL_SHIFT) |
(1<<CGU_AUTOBLOCK_CLOCK_BIT);
/* Disable SSP before to configure it */
SSP_CR1(ssp_port) = 0x0;
@ -105,7 +102,8 @@ void ssp_init(ssp_num_t ssp_num,
/* Configure SSP */
clock = serial_clock_rate;
SSP_CPSR(ssp_port) = clk_prescale;
SSP_CR0(ssp_port) = (data_size | frame_format | cpol_cpha_format | (clock<<8) );
SSP_CR0(ssp_port) =
(data_size | frame_format | cpol_cpha_format | (clock<<8));
/* Enable SSP */
SSP_CR1(ssp_port) = (SSP_ENABLE | mode | master_slave | slave_option);
@ -118,15 +116,14 @@ u16 ssp_read(ssp_num_t ssp_num)
{
u32 ssp_port;
if(ssp_num == SSP0_NUM)
{
if (ssp_num == SSP0_NUM) {
ssp_port = SSP0;
}else
{
} else {
ssp_port = SSP1;
}
/* Wait Until Data Received (Rx FIFO not Empty) */
while( (SSP_SR(ssp_port) & SSP_SR_RNE) == 0);
while ((SSP_SR(ssp_port) & SSP_SR_RNE) == 0);
return SSP_DR(ssp_port);
}
@ -135,15 +132,13 @@ void ssp_wait_until_not_busy(ssp_num_t ssp_num)
{
u32 ssp_port;
if(ssp_num == SSP0_NUM)
{
if (ssp_num == SSP0_NUM) {
ssp_port = SSP0;
}else
{
} else {
ssp_port = SSP1;
}
while( (SSP_SR(ssp_port) & SSP_SR_BSY) );
while ((SSP_SR(ssp_port) & SSP_SR_BSY));
}
/* This Function Wait Data TX Ready, and Write Data to SSP */
@ -151,16 +146,14 @@ void ssp_write(ssp_num_t ssp_num, u16 data)
{
u32 ssp_port;
if(ssp_num == SSP0_NUM)
{
if (ssp_num == SSP0_NUM) {
ssp_port = SSP0;
}else
{
} else {
ssp_port = SSP1;
}
/* Wait Until FIFO not full */
while( (SSP_SR(ssp_port) & SSP_SR_TNF) == 0);
while ((SSP_SR(ssp_port) & SSP_SR_TNF) == 0);
SSP_DR(ssp_port) = data;

12
lib/lpc43xx/vector_chipset.c
View File

@ -22,21 +22,21 @@
extern unsigned _etext_ram, _text_ram, _etext_rom;
#define CREG_M4MEMMAP MMIO32( (0x40043000 + 0x100) )
#define CREG_M4MEMMAP MMIO32((0x40043000 + 0x100))
static void pre_main(void)
{
volatile unsigned *src, *dest;
/* Copy the code from ROM to Real RAM (if enabled) */
if( (&_etext_ram-&_text_ram) > 0 )
{
if ((&_etext_ram-&_text_ram) > 0) {
src = &_etext_rom-(&_etext_ram-&_text_ram);
/* Change Shadow memory to ROM (for Debug Purpose in case Boot has not set correctly the M4MEMMAP because of debug) */
/* Change Shadow memory to ROM (for Debug Purpose in case Boot
* has not set correctly the M4MEMMAP because of debug)
*/
CREG_M4MEMMAP = (unsigned long)src;
for(dest = &_text_ram; dest < &_etext_ram; )
{
for (dest = &_text_ram; dest < &_etext_ram; ) {
*dest++ = *src++;
}

10
lib/sam/common/gpio.c
View File

@ -42,15 +42,17 @@ void gpio_init(u32 port, u32 pins, enum gpio_flags flags)
PIO_PDR(port) = pins;
}
if (flags & GPIO_FLAG_OPEN_DRAIN)
if (flags & GPIO_FLAG_OPEN_DRAIN) {
PIO_MDER(port) = pins;
else
} else {
PIO_MDDR(port) = pins;
}
if (flags & GPIO_FLAG_PULL_UP)
if (flags & GPIO_FLAG_PULL_UP) {
PIO_PUER(port) = pins;
else
} else {
PIO_PUDR(port) = pins;
}
}
void gpio_toggle(u32 gpioport, u32 gpios)

10
lib/sam/common/pmc.c
View File

@ -44,18 +44,20 @@ void pmc_plla_config(u8 mul, u8 div)
void pmc_peripheral_clock_enable(u8 pid)
{
if (pid < 32)
if (pid < 32) {
PMC_PCER0 = 1 << pid;
else
} else {
PMC_PCER1 = 1 << (pid & 31);
}
}
void pmc_peripheral_clock_disable(u8 pid)
{
if (pid < 32)
if (pid < 32) {
PMC_PCDR0 = 1 << pid;
else
} else {
PMC_PCDR1 = 1 << (pid & 31);
}
}
void pmc_mck_set_source(enum mck_src src)

4
lib/sam/common/usart.c
View File

@ -46,8 +46,8 @@ void usart_set_mode(u32 usart, enum usart_mode mode)
{
USART_CR(usart) =
(mode & USART_MODE_RX) ? USART_CR_RXEN : USART_CR_RXDIS;
USART_CR(usart) =
(mode & USART_MODE_TX) ? USART_CR_TXEN : USART_CR_TXDIS;
USART_CR(usart) = (mode & USART_MODE_TX) ? USART_CR_TXEN
: USART_CR_TXDIS;
}
void usart_set_flow_control(u32 usart, enum usart_flowcontrol fc)

103
lib/stm32/can.c
View File

@ -59,13 +59,15 @@ LGPL License Terms @ref lgpl_license
*/
#define CAN_MSR_INAK_TIMEOUT 0x0000FFFF
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Reset
The CAN peripheral and all its associated configuration registers are placed in the
reset condition. The reset is effective via the RCC peripheral reset system.
The CAN peripheral and all its associated configuration registers are placed in
the reset condition. The reset is effective via the RCC peripheral reset
system.
@param[in] canport Unsigned int32. CAN block register address base @ref can_reg_base.
@param[in] canport Unsigned int32. CAN block register address base @ref
can_reg_base.
*/
void can_reset(u32 canport)
{
@ -78,7 +80,7 @@ void can_reset(u32 canport)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Init
Initialize the selected CAN peripheral block.
@ -112,11 +114,10 @@ int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
/* Wait for acknowledge. */
wait_ack = CAN_MSR_INAK_TIMEOUT;
while ((--wait_ack) &&
((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK)) {
}
((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK));
/* Check the acknowledge. */
if ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK){
if ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK) {
return 1;
}
@ -126,61 +127,52 @@ int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
/* Set the automatic bus-off management. */
if (ttcm) {
CAN_MCR(canport) |= CAN_MCR_TTCM;
}
else {
} else {
CAN_MCR(canport) &= ~CAN_MCR_TTCM;
}
if (abom) {
CAN_MCR(canport) |= CAN_MCR_ABOM;
}
else {
} else {
CAN_MCR(canport) &= ~CAN_MCR_ABOM;
}
if (awum) {
CAN_MCR(canport) |= CAN_MCR_AWUM;
}
else {
} else {
CAN_MCR(canport) &= ~CAN_MCR_AWUM;
}
if (nart) {
CAN_MCR(canport) |= CAN_MCR_NART;
}
else{
} else {
CAN_MCR(canport) &= ~CAN_MCR_NART;
}
if (rflm) {
CAN_MCR(canport) |= CAN_MCR_RFLM;
}
else {
} else {
CAN_MCR(canport) &= ~CAN_MCR_RFLM;
}
if (txfp) {
CAN_MCR(canport) |= CAN_MCR_TXFP;
}
else {
} else {
CAN_MCR(canport) &= ~CAN_MCR_TXFP;
}
if (silent) {
CAN_BTR(canport) |= CAN_BTR_SILM;
}
else {
} else {
CAN_BTR(canport) &= ~CAN_BTR_SILM;
}
if (loopback) {
CAN_BTR(canport) |= CAN_BTR_LBKM;
}
else {
} else {
CAN_BTR(canport) &= ~CAN_BTR_LBKM;
}
/* Set bit timings. */
CAN_BTR(canport) |= sjw | ts2 | ts1 |
((brp - 1ul) & CAN_BTR_BRP_MASK);
@ -191,8 +183,7 @@ int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
/* Wait for acknowledge. */
wait_ack = CAN_MSR_INAK_TIMEOUT;
while ((--wait_ack) &&
((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK)) {
}
((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK));
if ((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK) {
ret = 1;
@ -201,7 +192,7 @@ int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
return ret;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Filter Init
Initialize incoming message filter and assign to FIFO.
@ -251,10 +242,10 @@ void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
/* Select FIFO0 or FIFO1 as filter assignement. */
if (fifo) {
CAN_FFA1R(canport) |= filter_select_bit; /* FIFO1 */
}
else {
} else {
CAN_FFA1R(canport) &= ~filter_select_bit; /* FIFO0 */
}
if (enable) {
CAN_FA1R(canport) |= filter_select_bit; /* Activate filter. */
}
@ -263,7 +254,7 @@ void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
CAN_FMR(canport) &= ~CAN_FMR_FINIT;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Initialize a 16bit Message ID Mask Filter
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@ -283,7 +274,7 @@ void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1,
((u32)id2 << 16) | (u32)mask2, fifo, enable);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Initialize a 32bit Message ID Mask Filter
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@ -299,7 +290,7 @@ void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask,
can_filter_init(canport, nr, true, false, id, mask, fifo, enable);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Initialize a 16bit Message ID List Filter
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@ -319,7 +310,7 @@ void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2,
((u32)id3 << 16) | (u32)id4, fifo, enable);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Initialize a 32bit Message ID List Filter
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@ -335,7 +326,7 @@ void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2,
can_filter_init(canport, nr, true, true, id1, id2, fifo, enable);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Enable IRQ
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@ -346,7 +337,7 @@ void can_enable_irq(u32 canport, u32 irq)
CAN_IER(canport) |= irq;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Disable IRQ
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@ -357,7 +348,7 @@ void can_disable_irq(u32 canport, u32 irq)
CAN_IER(canport) &= ~irq;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Transmit Message
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@ -376,7 +367,7 @@ int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data)
union {
u8 data8[4];
u32 data32;
}tdlxr,tdhxr;
} tdlxr, tdhxr;
/* Check which transmit mailbox is empty if any. */
if ((CAN_TSR(canport) & CAN_TSR_TME0) == CAN_TSR_TME0) {
@ -394,27 +385,28 @@ int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data)
/* If we have no empty mailbox return with an error. */
if (ret == -1) {
return ret;
}
if (ext) {
/* Set extended ID. */
CAN_TIxR(canport, mailbox) = (id << CAN_TIxR_EXID_SHIFT) | CAN_TIxR_IDE;
CAN_TIxR(canport, mailbox) = (id << CAN_TIxR_EXID_SHIFT) |
CAN_TIxR_IDE;
} else {
/* Set standard ID. */
CAN_TIxR(canport, mailbox) = id << CAN_TIxR_STID_SHIFT;
}
/* Set/clear remote transmission request bit. */
if (rtr){
if (rtr) {
CAN_TIxR(canport, mailbox) |= CAN_TIxR_RTR; /* Set */
}
/* Set the DLC. */
CAN_TDTxR(canport, mailbox) &= ~CAN_TDTxR_DLC_MASK;
CAN_TDTxR(canport, mailbox) |= (length & CAN_TDTxR_DLC_MASK);
switch(length) {
switch (length) {
case 8:
tdhxr.data8[3] = data[7];
/* no break */
@ -453,7 +445,7 @@ int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data)
return ret;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Release FIFO
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@ -463,13 +455,12 @@ void can_fifo_release(u32 canport, u8 fifo)
{
if (fifo == 0) {
CAN_RF0R(canport) |= CAN_RF1R_RFOM1;
}
else {
} else {
CAN_RF1R(canport) |= CAN_RF1R_RFOM1;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CAN Receive Message
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@ -489,8 +480,8 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
union {
u8 data8[4];
u32 data32;
}rdlxr,rdhxr;
const u32 fifoid_array[2] = {CAN_FIFO0,CAN_FIFO1};
} rdlxr, rdhxr;
const u32 fifoid_array[2] = {CAN_FIFO0, CAN_FIFO1};
fifo_id = fifoid_array[fifo];
@ -498,18 +489,19 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_IDE) {
*ext = true;
/* Get extended CAN ID. */
*id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_EXID_SHIFT) & CAN_RIxR_EXID_MASK;
*id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_EXID_SHIFT) &
CAN_RIxR_EXID_MASK;
} else {
*ext = false;
/* Get standard CAN ID. */
*id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_STID_SHIFT) & CAN_RIxR_STID_MASK;
*id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_STID_SHIFT) &
CAN_RIxR_STID_MASK;
}
/* Get remote transmit flag. */
if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_RTR) {
*rtr = true;
}
else {
} else {
*rtr = false;
}
@ -519,8 +511,9 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
/* Get data length. */
*length = CAN_RDTxR(canport, fifo_id) & CAN_RDTxR_DLC_MASK;
/* accelerate reception by copying the CAN data from the controller memory to
* the fast internal RAM */
/* accelerate reception by copying the CAN data from the controller
* memory to the fast internal RAM
*/
rdlxr.data32 = CAN_RDLxR(canport, fifo_id);
rdhxr.data32 = CAN_RDHxR(canport, fifo_id);
@ -546,7 +539,7 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
data[7] = rdhxr.data8[3];
/* Release the FIFO. */
if (release){
if (release) {
can_fifo_release(canport, fifo);
}
}

10
lib/stm32/common/crc_common_all.c
View File

@ -27,7 +27,7 @@
/**@{*/
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CRC Reset.
Reset the CRC unit and forces the data register to all 1s.
@ -39,7 +39,7 @@ void crc_reset(void)
CRC_CR |= CRC_CR_RESET;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CRC Calculate.
Writes a data word to the register, the write operation stalling until the
@ -52,11 +52,11 @@ computation is complete.
u32 crc_calculate(u32 data)
{
CRC_DR = data;
// Data sheet says this blocks until it's ready....
/* Data sheet says this blocks until it's ready.... */
return CRC_DR;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief CRC Calculate of a Block of Data.
Writes data words consecutively to the register, the write operation stalling
@ -70,9 +70,11 @@ until the computation of each word is complete.
u32 crc_calculate_block(u32 *datap, int size)
{
int i;
for (i = 0; i < size; i++) {
CRC_DR = datap[i];
}
return CRC_DR;
}
/**@}*/

121
lib/stm32/common/dac_common_all.c
View File

@ -120,12 +120,12 @@ LGPL License Terms @ref lgpl_license
#define MASK8 0xFF
#define MASK12 0xFFF
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DAC Channel Enable.
Enable a digital to analog converter channel. After setting this enable, the DAC
requires a t<sub>wakeup</sub> time typically around 10 microseconds before it
actually wakes up.
Enable a digital to analog converter channel. After setting this enable, the
DAC requires a t<sub>wakeup</sub> time typically around 10 microseconds before
it actually wakes up.
@param[in] dac_channel enum ::data_channel.
*/
@ -145,7 +145,7 @@ void dac_enable(data_channel dac_channel)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DAC Channel Disable.
Disable a digital to analog converter channel.
@ -168,13 +168,13 @@ void dac_disable(data_channel dac_channel)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DAC Channel Output Buffer Enable.
Enable a digital to analog converter channel output drive buffer. This is an optional
amplifying buffer that provides additional drive for the output signal. The
buffer is enabled by default after a reset and needs to be explicitly disabled
if required.
Enable a digital to analog converter channel output drive buffer. This is an
optional amplifying buffer that provides additional drive for the output
signal. The buffer is enabled by default after a reset and needs to be
explicitly disabled if required.
@param[in] dac_channel enum ::data_channel.
*/
@ -193,12 +193,12 @@ void dac_buffer_enable(data_channel dac_channel)
break;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DAC Channel Output Buffer Disable.
Disable a digital to analog converter channel output drive buffer. Disabling this will
reduce power consumption slightly and will increase the output impedance of the DAC.
The buffers are enabled by default after a reset.
Disable a digital to analog converter channel output drive buffer. Disabling
this will reduce power consumption slightly and will increase the output
impedance of the DAC. The buffers are enabled by default after a reset.
@param[in] dac_channel enum ::data_channel.
*/
@ -217,7 +217,7 @@ void dac_buffer_disable(data_channel dac_channel)
break;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DAC Channel DMA Enable.
Enable a digital to analog converter channel DMA mode (connected to DMA2 channel
@ -242,7 +242,7 @@ void dac_dma_enable(data_channel dac_channel)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DAC Channel DMA Disable.
Disable a digital to analog converter channel DMA mode.
@ -265,13 +265,13 @@ void dac_dma_disable(data_channel dac_channel)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DAC Channel Trigger Enable.
Enable a digital to analog converter channel external trigger mode. This allows an
external trigger to initiate register transfers from the buffer register to the DAC
output register, followed by a DMA transfer to the buffer register if DMA is enabled.
The trigger source must also be selected.
Enable a digital to analog converter channel external trigger mode. This allows
an external trigger to initiate register transfers from the buffer register to
the DAC output register, followed by a DMA transfer to the buffer register if
DMA is enabled. The trigger source must also be selected.
@param[in] dac_channel enum ::data_channel.
*/
@ -291,7 +291,7 @@ void dac_trigger_enable(data_channel dac_channel)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DAC Channel Trigger Disable.
Disable a digital to analog converter channel external trigger.
@ -314,14 +314,15 @@ void dac_trigger_disable(data_channel dac_channel)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Set DAC Channel Trigger Source.
Sets the digital to analog converter trigger source, which can be taken from various
timers, an external trigger or a software trigger.
Sets the digital to analog converter trigger source, which can be taken from
various timers, an external trigger or a software trigger.
@param[in] dac_trig_src u32. Taken from @ref dac_trig2_sel or @ref dac_trig1_sel or
a logical OR of one of each of these to set both channels simultaneously.
@param[in] dac_trig_src u32. Taken from @ref dac_trig2_sel or @ref
dac_trig1_sel or a logical OR of one of each of these to set both channels
simultaneously.
*/
void dac_set_trigger_source(u32 dac_trig_src)
@ -329,17 +330,17 @@ void dac_set_trigger_source(u32 dac_trig_src)
DAC_CR |= dac_trig_src;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Enable and Set DAC Channel Waveform Generation.
Enable the digital to analog converter waveform generation as either pseudo-random
noise or triangular wave. These signals are superimposed on existing output values
in the DAC output registers.
Enable the digital to analog converter waveform generation as either
pseudo-random noise or triangular wave. These signals are superimposed on
existing output values in the DAC output registers.
@note The DAC trigger must be enabled for this to work.
@param[in] dac_wave_ens u32. Taken from @ref dac_wave1_en or @ref dac_wave2_en or
a logical OR of one of each of these to set both channels simultaneously.
@param[in] dac_wave_ens u32. Taken from @ref dac_wave1_en or @ref dac_wave2_en
or a logical OR of one of each of these to set both channels simultaneously.
*/
void dac_set_waveform_generation(u32 dac_wave_ens)
@ -347,7 +348,7 @@ void dac_set_waveform_generation(u32 dac_wave_ens)
DAC_CR |= dac_wave_ens;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Disable DAC Channel Waveform Generation.
Disable a digital to analog converter channel superimposed waveform generation.
@ -370,22 +371,24 @@ void dac_disable_waveform_generation(data_channel dac_channel)
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Set DAC Channel LFSR Mask or Triangle Wave Amplitude.
Sets the digital to analog converter superimposed waveform generation characteristics.
@li If the noise generation mode is set, this sets the length of the PRBS sequence and
hence the amplitude of the output noise signal. Default setting is length 1.
@li If the triangle wave generation mode is set, this sets the amplitude of the
output signal as 2^(n)-1 where n is the parameter value. Default setting is 1.
Sets the digital to analog converter superimposed waveform generation
characteristics. @li If the noise generation mode is set, this sets the length
of the PRBS sequence and hence the amplitude of the output noise signal.
Default setting is length 1. @li If the triangle wave generation mode is set,
this sets the amplitude of the output signal as 2^(n)-1 where n is the
parameter value. Default setting is 1.
@note High amplitude levels of these waveforms can overload the DAC and distort the
signal output.
@note This must be called before enabling the DAC as the settings will then become read-only.
@note High amplitude levels of these waveforms can overload the DAC and distort
the signal output.
@note This must be called before enabling the DAC as the settings will then
become read-only.
@note The DAC trigger must be enabled for this to work.
@param[in] dac_mamp u32. Taken from @ref dac_mamp2 or @ref dac_mamp1 or a logical OR
of one of each of these to set both channels simultaneously.
@param[in] dac_mamp u32. Taken from @ref dac_mamp2 or @ref dac_mamp1 or a
logical OR of one of each of these to set both channels simultaneously.
*/
void dac_set_waveform_characteristics(u32 dac_mamp)
@ -393,7 +396,7 @@ void dac_set_waveform_characteristics(u32 dac_mamp)
DAC_CR |= dac_mamp;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Load DAC Data Register.
Loads the appropriate digital to analog converter data register with 12 or 8 bit
@ -407,10 +410,10 @@ data to be converted on a channel. The data can be aligned as follows:
@param[in] dac_channel enum ::data_channel.
*/
void dac_load_data_buffer_single(u16 dac_data, data_align dac_data_format, data_channel dac_channel)
void dac_load_data_buffer_single(u16 dac_data, data_align dac_data_format,
data_channel dac_channel)
{
if (dac_channel == CHANNEL_1)
{
if (dac_channel == CHANNEL_1) {
switch (dac_data_format) {
case RIGHT8:
DAC_DHR8R1 = dac_data;
@ -422,9 +425,7 @@ void dac_load_data_buffer_single(u16 dac_data, data_align dac_data_format, data_
DAC_DHR12L1 = dac_data;
break;
}
}
else if (dac_channel == CHANNEL_2)
{
} else if (dac_channel == CHANNEL_2) {
switch (dac_data_format) {
case RIGHT8:
DAC_DHR8R2 = dac_data;
@ -439,7 +440,7 @@ void dac_load_data_buffer_single(u16 dac_data, data_align dac_data_format, data_
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Load DAC Dual Data Register.
Loads the appropriate digital to analog converter dual data register with 12 or
@ -449,25 +450,29 @@ identically.
@param[in] dac_data1 u16 for channel 1 with appropriate alignment.
@param[in] dac_data2 u16 for channel 2 with appropriate alignment.
@param[in] dac_data_format enum ::data_align. Right or left aligned, and 8 or 12 bit.
@param[in] dac_data_format enum ::data_align. Right or left aligned, and 8 or
12 bit.
*/
void dac_load_data_buffer_dual(u16 dac_data1, u16 dac_data2, data_align dac_data_format)
void dac_load_data_buffer_dual(u16 dac_data1, u16 dac_data2,
data_align dac_data_format)
{
switch (dac_data_format) {
case RIGHT8:
DAC_DHR8RD = ((dac_data1 & MASK8) | ((dac_data2 & MASK8) << 8));
break;
case RIGHT12:
DAC_DHR12RD = ((dac_data1 & MASK12) | ((dac_data2 & MASK12) << 16));
DAC_DHR12RD = ((dac_data1 & MASK12) |
((dac_data2 & MASK12) << 16));
break;
case LEFT12:
DAC_DHR12LD = ((dac_data1 & MASK12) | ((dac_data2 & MASK12) << 16));
DAC_DHR12LD = ((dac_data1 & MASK12) |
((dac_data2 & MASK12) << 16));
break;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Trigger the DAC by a Software Trigger.
If the trigger source is set to be a software trigger, cause a trigger to occur.

88
lib/stm32/common/dma_common_f13.c
View File

@ -40,7 +40,7 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/stm32/dma.h>
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Reset
The channel is disabled and configuration registers are cleared.
@ -63,7 +63,7 @@ void dma_channel_reset(u32 dma, u8 channel)
DMA_IFCR(dma) |= DMA_IFCR_CIF(channel);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Clear Interrupt Flag
The interrupt flag for the channel is cleared. More than one interrupt for the
@ -71,7 +71,8 @@ same channel may be cleared by using the logical OR of the interrupt flags.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: @ref dma_ch
@param[in] interrupts unsigned int32. Logical OR of interrupt numbers: @ref dma_if_offset
@param[in] interrupts unsigned int32. Logical OR of interrupt numbers: @ref
dma_if_offset
*/
void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts)
@ -81,7 +82,7 @@ void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts)
DMA_IFCR(dma) = flags;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Read Interrupt Flag
The interrupt flag for the channel is returned.
@ -99,7 +100,7 @@ bool dma_get_interrupt_flag(u32 dma, u8 channel, u32 interrupt)
return ((DMA_ISR(dma) & flag) > 0);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Memory to Memory Transfers
Memory to memory transfers do not require a trigger to activate each transfer.
@ -116,7 +117,7 @@ void dma_enable_mem2mem_mode(u32 dma, u8 channel)
DMA_CCR(dma, channel) &= ~DMA_CCR_CIRC;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Set Priority
Channel Priority has four levels: low to very high. This has precedence over the
@ -133,7 +134,7 @@ void dma_set_priority(u32 dma, u8 channel, u32 prio)
DMA_CCR(dma, channel) |= prio;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Set Memory Word Width
Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
@ -151,16 +152,17 @@ void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size)
DMA_CCR(dma, channel) |= mem_size;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Set Peripheral Word Width
Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
alignment information if the source and destination widths do not match, or
Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet
for alignment information if the source and destination widths do not match, or
if the peripheral does not support byte or half-word writes.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
@param[in] peripheral_size unsigned int32. Peripheral word width @ref dma_ch_perwidth.
@param[in] peripheral_size unsigned int32. Peripheral word width @ref
dma_ch_perwidth.
*/
void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size)
@ -169,7 +171,7 @@ void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size)
DMA_CCR(dma, channel) |= peripheral_size;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Memory Increment after Transfer
Following each transfer the current memory address is incremented by
@ -185,7 +187,7 @@ void dma_enable_memory_increment_mode(u32 dma, u8 channel)
DMA_CCR(dma, channel) |= DMA_CCR_MINC;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Disable Memory Increment after Transfer
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -197,7 +199,7 @@ void dma_disable_memory_increment_mode(u32 dma, u8 channel)
DMA_CCR(dma, channel) &= ~DMA_CCR_MINC;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Peripheral Increment after Transfer
Following each transfer the current peripheral address is incremented by
@ -213,7 +215,7 @@ void dma_enable_peripheral_increment_mode(u32 dma, u8 channel)
DMA_CCR(dma, channel) |= DMA_CCR_PINC;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Disable Peripheral Increment after Transfer
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -225,7 +227,7 @@ void dma_disable_peripheral_increment_mode(u32 dma, u8 channel)
DMA_CCR(dma, channel) &= ~DMA_CCR_PINC;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Memory Circular Mode
After the number of bytes/words to be transferred has been completed, the
@ -245,7 +247,7 @@ void dma_enable_circular_mode(u32 dma, u8 channel)
DMA_CCR(dma, channel) &= ~DMA_CCR_MEM2MEM;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Transfers from a Peripheral
The data direction is set to read from a peripheral.
@ -259,7 +261,7 @@ void dma_set_read_from_peripheral(u32 dma, u8 channel)
DMA_CCR(dma, channel) &= ~DMA_CCR_DIR;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Transfers from Memory
The data direction is set to read from memory.
@ -273,7 +275,7 @@ void dma_set_read_from_memory(u32 dma, u8 channel)
DMA_CCR(dma, channel) |= DMA_CCR_DIR;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Interrupt on Transfer Error
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -285,7 +287,7 @@ void dma_enable_transfer_error_interrupt(u32 dma, u8 channel)
DMA_CCR(dma, channel) |= DMA_CCR_TEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Disable Interrupt on Transfer Error
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -297,7 +299,7 @@ void dma_disable_transfer_error_interrupt(u32 dma, u8 channel)
DMA_CCR(dma, channel) &= ~DMA_CCR_TEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Interrupt on Transfer Half Complete
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -309,7 +311,7 @@ void dma_enable_half_transfer_interrupt(u32 dma, u8 channel)
DMA_CCR(dma, channel) |= DMA_CCR_HTIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Disable Interrupt on Transfer Half Complete
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -321,7 +323,7 @@ void dma_disable_half_transfer_interrupt(u32 dma, u8 channel)
DMA_CCR(dma, channel) &= ~DMA_CCR_HTIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Interrupt on Transfer Complete
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -333,7 +335,7 @@ void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel)
DMA_CCR(dma, channel) |= DMA_CCR_TCIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Disable Interrupt on Transfer Complete
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -345,7 +347,7 @@ void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel)
DMA_CCR(dma, channel) &= ~DMA_CCR_TCIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -357,10 +359,11 @@ void dma_enable_channel(u32 dma, u8 channel)
DMA_CCR(dma, channel) |= DMA_CCR_EN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Disable
@note The DMA channel registers retain their values when the channel is disabled.
@note The DMA channel registers retain their values when the channel is
disabled.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
@ -371,14 +374,14 @@ void dma_disable_channel(u32 dma, u8 channel)
DMA_CCR(dma, channel) &= ~DMA_CCR_EN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Set the Peripheral Address
Set the address of the peripheral register to or from which data is to be transferred.
Refer to the documentation for the specific peripheral.
Set the address of the peripheral register to or from which data is to be
transferred. Refer to the documentation for the specific peripheral.
@note The DMA channel must be disabled before setting this address. This function
has no effect if the channel is enabled.
@note The DMA channel must be disabled before setting this address. This
function has no effect if the channel is enabled.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
@ -387,15 +390,16 @@ has no effect if the channel is enabled.
void dma_set_peripheral_address(u32 dma, u8 channel, u32 address)
{
if (!(DMA_CCR(dma, channel) & DMA_CCR_EN))
if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) {
DMA_CPAR(dma, channel) = (u32) address;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Set the Base Memory Address
@note The DMA channel must be disabled before setting this address. This function
has no effect if the channel is enabled.
@note The DMA channel must be disabled before setting this address. This
function has no effect if the channel is enabled.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
@ -404,19 +408,21 @@ has no effect if the channel is enabled.
void dma_set_memory_address(u32 dma, u8 channel, u32 address)
{
if (!(DMA_CCR(dma, channel) & DMA_CCR_EN))
if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) {
DMA_CMAR(dma, channel) = (u32) address;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Set the Transfer Block Size
@note The DMA channel must be disabled before setting this count value. The count
is not changed if the channel is enabled.
@note The DMA channel must be disabled before setting this count value. The
count is not changed if the channel is enabled.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
@param[in] number unsigned int16. Number of data words to transfer (65535 maximum).
@param[in] number unsigned int16. Number of data words to transfer (65535
maximum).
*/
void dma_set_number_of_data(u32 dma, u8 channel, u16 number)

184
lib/stm32/common/dma_common_f24.c
View File

@ -1,6 +1,7 @@
/** @addtogroup dma_file
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
This library supports the DMA Control System in the STM32F2 and STM32F4
series of ARM Cortex Microcontrollers by ST Microelectronics.
@ -47,7 +48,7 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/stm32/dma.h>
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Reset
The specified stream is disabled and configuration registers are cleared.
@ -72,17 +73,14 @@ void dma_stream_reset(u32 dma, u8 stream)
DMA_SFCR(dma, stream) = 0x21;
/* Reset all stream interrupt flags using the interrupt flag clear register. */
u32 mask = DMA_ISR_MASK(stream);
if (stream < 4)
{
if (stream < 4) {
DMA_LIFCR(dma) |= mask;
}
else
{
} else {
DMA_HIFCR(dma) |= mask;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Clear Interrupt Flag
The interrupt flag for the stream is cleared. More than one interrupt for the
@ -90,25 +88,25 @@ same stream may be cleared by using the bitwise OR of the interrupt flags.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
@param[in] interrupts unsigned int32. Bitwise OR of interrupt numbers: @ref dma_if_offset
@param[in] interrupts unsigned int32. Bitwise OR of interrupt numbers: @ref
dma_if_offset
*/
void dma_clear_interrupt_flags(u32 dma, u8 stream, u32 interrupts)
{
/* Get offset to interrupt flag location in stream field */
/* Get offset to interrupt flag location in stream field */
u32 flags = (interrupts << DMA_ISR_OFFSET(stream));
/* First four streams are in low register. Flag clear must be set then reset. */
if (stream < 4)
{
/* First four streams are in low register. Flag clear must be set then
* reset.
*/
if (stream < 4) {
DMA_LIFCR(dma) = flags;
}
else
{
} else {
DMA_HIFCR(dma) = flags;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Read Interrupt Flag
The interrupt flag for the stream is returned.
@ -121,15 +119,19 @@ The interrupt flag for the stream is returned.
bool dma_get_interrupt_flag(u32 dma, u8 stream, u32 interrupt)
{
/* get offset to interrupt flag location in stream field.
Assumes stream and interrupt parameters are integers */
/* get offset to interrupt flag location in stream field. Assumes
* stream and interrupt parameters are integers.
*/
u32 flag = (interrupt << DMA_ISR_OFFSET(stream));
/* First four streams are in low register */
if (stream < 4) return ((DMA_LISR(dma) & flag) > 0);
else return ((DMA_HISR(dma) & flag) > 0);
/* First four streams are in low register */
if (stream < 4) {
return ((DMA_LISR(dma) & flag) > 0);
} else {
return ((DMA_HISR(dma) & flag) > 0);
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable Transfer Direction
Set peripheral to memory, memory to peripheral or memory to memory. If memory
@ -146,16 +148,18 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
void dma_set_transfer_mode(u32 dma, u8 stream, u32 direction)
{
u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_DIR_MASK);
/* Disable circular and double buffer modes if memory to memory transfers
are in effect (Direct Mode is automatically disabled by hardware) */
if (direction == DMA_SxCR_DIR_MEM_TO_MEM)
{
/* Disable circular and double buffer modes if memory to memory
* transfers are in effect. (Direct Mode is automatically disabled by
* hardware)
*/
if (direction == DMA_SxCR_DIR_MEM_TO_MEM) {
reg32 &= ~(DMA_SxCR_CIRC | DMA_SxCR_DBM);
}
DMA_SCR(dma, stream) = (reg32 | direction);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set Priority
Stream Priority has four levels: low to very high. This has precedence over the
@ -175,7 +179,7 @@ void dma_set_priority(u32 dma, u8 stream, u32 prio)
DMA_SCR(dma, stream) |= prio;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set Memory Word Width
Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
@ -190,23 +194,23 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
void dma_set_memory_size(u32 dma, u8 stream, u32 mem_size)
{
DMA_SCR(dma, stream) &= ~(DMA_SxCR_MSIZE_MASK);
DMA_SCR(dma, stream) |= mem_size;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set Peripheral Word Width
Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
alignment information if the source and destination widths do not match, or
Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet
for alignment information if the source and destination widths do not match, or
if the peripheral does not support byte or half-word writes.
Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
@param[in] peripheral_size unsigned int32. Peripheral word width @ref dma_st_perwidth.
@param[in] peripheral_size unsigned int32. Peripheral word width @ref
dma_st_perwidth.
*/
void dma_set_peripheral_size(u32 dma, u8 stream, u32 peripheral_size)
@ -215,7 +219,7 @@ void dma_set_peripheral_size(u32 dma, u8 stream, u32 peripheral_size)
DMA_SCR(dma, stream) |= peripheral_size;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable Memory Increment after Transfer
Following each transfer the current memory address is incremented by
@ -233,7 +237,7 @@ void dma_enable_memory_increment_mode(u32 dma, u8 stream)
DMA_SCR(dma, stream) |= DMA_SxCR_MINC;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Disable Memory Increment after Transfer
Ensure that the stream is disabled otherwise the setting will not be changed.
@ -247,7 +251,7 @@ void dma_disable_memory_increment_mode(u32 dma, u8 stream)
DMA_SCR(dma, stream) &= ~DMA_SxCR_MINC;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Variable Sized Peripheral Increment after Transfer
Following each transfer the current peripheral address is incremented by
@ -266,7 +270,7 @@ void dma_enable_peripheral_increment_mode(u32 dma, u8 stream)
DMA_SCR(dma, stream) = (reg32 & ~DMA_SxCR_PINCOS);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Disable Peripheral Increment after Transfer
Ensure that the stream is disabled otherwise the setting will not be changed.
@ -280,7 +284,7 @@ void dma_disable_peripheral_increment_mode(u32 dma, u8 stream)
DMA_SCR(dma, stream) &= ~DMA_SxCR_PINC;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Fixed Sized Peripheral Increment after Transfer
Following each transfer the current peripheral address is incremented by
@ -298,7 +302,7 @@ void dma_enable_fixed_peripheral_increment_mode(u32 dma, u8 stream)
DMA_SCR(dma, stream) |= (DMA_SxCR_PINC | DMA_SxCR_PINCOS);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable Memory Circular Mode
After the number of bytes/words to be transferred has been completed, the
@ -320,7 +324,7 @@ void dma_enable_circular_mode(u32 dma, u8 stream)
DMA_SCR(dma, stream) |= DMA_SxCR_CIRC;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Channel Select
Associate an input channel to the stream. Not every channel is allocated to a
@ -339,7 +343,7 @@ void dma_channel_select(u32 dma, u8 stream, u32 channel)
DMA_SCR(dma, stream) |= channel;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set Memory Burst Configuration
Set the memory burst type to none, 4 8 or 16 word length. This is forced to none
@ -358,7 +362,7 @@ void dma_set_memory_burst(u32 dma, u8 stream, u32 burst)
DMA_SCR(dma, stream) = (reg32 | burst);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set Peripheral Burst Configuration
Set the memory burst type to none, 4 8 or 16 word length. This is forced to none
@ -377,11 +381,11 @@ void dma_set_peripheral_burst(u32 dma, u8 stream, u32 burst)
DMA_SCR(dma, stream) = (reg32 | burst);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set Initial Target Memory
In double buffered mode, set the target memory (M0 or M1) to be used for the first
transfer.
In double buffered mode, set the target memory (M0 or M1) to be used for the
first transfer.
Ensure that the stream is disabled otherwise the setting will not be changed.
@ -393,17 +397,20 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
void dma_set_initial_target(u32 dma, u8 stream, u8 memory)
{
u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_CT);
if (memory == 1) reg32 |= DMA_SxCR_CT;
if (memory == 1) {
reg32 |= DMA_SxCR_CT;
}
DMA_SCR(dma, stream) = reg32;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Read Current Memory Target
In double buffer mode, return the current memory target (M0 or M1). It is possible
to update the memory pointer in the register that is <b> not </b> currently in
use. An attempt to change the register currently in use will cause the stream
to be disabled and the transfer error flag to be set.
In double buffer mode, return the current memory target (M0 or M1). It is
possible to update the memory pointer in the register that is <b> not </b>
currently in use. An attempt to change the register currently in use will cause
the stream to be disabled and the transfer error flag to be set.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
@ -412,11 +419,14 @@ to be disabled and the transfer error flag to be set.
u8 dma_get_target(u32 dma, u8 stream)
{
if (DMA_SCR(dma, stream) & DMA_SxCR_CT) return 1;
if (DMA_SCR(dma, stream) & DMA_SxCR_CT) {
return 1;
}
return 0;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable Double Buffer Mode
Double buffer mode is used for memory to/from peripheral transfers only, and in
@ -436,7 +446,7 @@ void dma_enable_double_buffer_mode(u32 dma, u8 stream)
DMA_SCR(dma, stream) |= DMA_SxCR_DBM;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Disable Double Buffer Mode
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -448,7 +458,7 @@ void dma_disable_double_buffer_mode(u32 dma, u8 stream)
DMA_SCR(dma, stream) &= ~DMA_SxCR_DBM;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set Peripheral Flow Control
Set the peripheral to control DMA flow. Useful when the number of transfers is
@ -465,7 +475,7 @@ void dma_set_peripheral_flow_control(u32 dma, u8 stream)
DMA_SCR(dma, stream) |= DMA_SxCR_PFCTRL;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set DMA Flow Control
Set the DMA controller to control DMA flow. This is the default.
@ -481,7 +491,7 @@ void dma_set_dma_flow_control(u32 dma, u8 stream)
DMA_SCR(dma, stream) &= ~DMA_SxCR_PFCTRL;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable Interrupt on Transfer Error
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -494,7 +504,7 @@ void dma_enable_transfer_error_interrupt(u32 dma, u8 stream)
DMA_SCR(dma, stream) |= DMA_SxCR_TEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Disable Interrupt on Transfer Error
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -506,7 +516,7 @@ void dma_disable_transfer_error_interrupt(u32 dma, u8 stream)
DMA_SCR(dma, stream) &= ~DMA_SxCR_TEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable Interrupt on Transfer Half Complete
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -519,7 +529,7 @@ void dma_enable_half_transfer_interrupt(u32 dma, u8 stream)
DMA_SCR(dma, stream) |= DMA_SxCR_HTIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Disable Interrupt on Transfer Half Complete
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -531,7 +541,7 @@ void dma_disable_half_transfer_interrupt(u32 dma, u8 stream)
DMA_SCR(dma, stream) &= ~DMA_SxCR_HTIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable Interrupt on Transfer Complete
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -544,7 +554,7 @@ void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream)
DMA_SCR(dma, stream) |= DMA_SxCR_TCIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Disable Interrupt on Transfer Complete
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -556,7 +566,7 @@ void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream)
DMA_SCR(dma, stream) &= ~DMA_SxCR_TCIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable Interrupt on Direct Mode Error
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -569,7 +579,7 @@ void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream)
DMA_SCR(dma, stream) |= DMA_SxCR_DMEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Disable Interrupt on Direct Mode Error
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -581,7 +591,7 @@ void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream)
DMA_SCR(dma, stream) &= ~DMA_SxCR_DMEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Enable Interrupt on FIFO Error
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -594,7 +604,7 @@ void dma_enable_fifo_error_interrupt(u32 dma, u8 stream)
DMA_SFCR(dma, stream) |= DMA_SxFCR_FEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Disable Interrupt on FIFO Error
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -606,7 +616,7 @@ void dma_disable_fifo_error_interrupt(u32 dma, u8 stream)
DMA_SFCR(dma, stream) &= ~DMA_SxFCR_FEIE;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Get FIFO Status
Status of FIFO (empty. full or partial filled states) is returned. This has no
@ -619,10 +629,10 @@ meaning if direct mode is enabled (as the FIFO is not used).
u32 dma_fifo_status(u32 dma, u8 stream)
{
return (DMA_SFCR(dma, stream) & DMA_SxFCR_FS_MASK);
return DMA_SFCR(dma, stream) & DMA_SxFCR_FS_MASK;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Enable Direct Mode
Direct mode is the default. Data is transferred as soon as a DMA request is
@ -638,7 +648,7 @@ void dma_enable_direct_mode(u32 dma, u8 stream)
DMA_SFCR(dma, stream) &= ~DMA_SxFCR_DMDIS;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Enable FIFO Mode
Data is transferred via a FIFO.
@ -652,7 +662,7 @@ void dma_enable_fifo_mode(u32 dma, u8 stream)
DMA_SFCR(dma, stream) |= DMA_SxFCR_DMDIS;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Set FIFO Threshold
This is the filled level at which data is transferred out of the FIFO to the
@ -669,7 +679,7 @@ void dma_set_fifo_threshold(u32 dma, u8 stream, u32 threshold)
DMA_SFCR(dma, stream) = (reg32 | threshold);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Enable
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@ -681,7 +691,7 @@ void dma_enable_stream(u32 dma, u8 stream)
DMA_SCR(dma, stream) |= DMA_SxCR_EN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Disable
@note The DMA stream registers retain their values when the stream is disabled.
@ -695,11 +705,11 @@ void dma_disable_stream(u32 dma, u8 stream)
DMA_SCR(dma, stream) &= ~DMA_SxCR_EN;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set the Peripheral Address
Set the address of the peripheral register to or from which data is to be transferred.
Refer to the documentation for the specific peripheral.
Set the address of the peripheral register to or from which data is to be
transferred. Refer to the documentation for the specific peripheral.
@note The DMA stream must be disabled before setting this address. This function
has no effect if the stream is enabled.
@ -711,11 +721,12 @@ has no effect if the stream is enabled.
void dma_set_peripheral_address(u32 dma, u8 stream, u32 address)
{
if (!(DMA_SCR(dma, stream) & DMA_SxCR_EN))
if (!(DMA_SCR(dma, stream) & DMA_SxCR_EN)) {
DMA_SPAR(dma, stream) = (u32 *) address;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set the Base Memory Address 0
Set the address pointer to the memory location for DMA transfers. The DMA stream
@ -733,11 +744,13 @@ This is the default base memory address used in direct mode.
void dma_set_memory_address(u32 dma, u8 stream, u32 address)
{
u32 reg32 = DMA_SCR(dma, stream);
if ( !(reg32 & DMA_SxCR_EN) || ((reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM)) )
if (!(reg32 & DMA_SxCR_EN) ||
((reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM))) {
DMA_SM0AR(dma, stream) = (u32 *) address;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set the Base Memory Address 1
Set the address pointer to the memory location for DMA transfers. The DMA stream
@ -753,11 +766,13 @@ to change this in double buffer mode when the current target is memory area 0
void dma_set_memory_address_1(u32 dma, u8 stream, u32 address)
{
u32 reg32 = DMA_SCR(dma, stream);
if ( !(reg32 & DMA_SxCR_EN) || (!(reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM)) )
if (!(reg32 & DMA_SxCR_EN) ||
(!(reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM))) {
DMA_SM1AR(dma, stream) = (u32 *) address;
}
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief DMA Stream Set the Transfer Block Size
@note The DMA stream must be disabled before setting this count value. The count
@ -765,7 +780,8 @@ is not changed if the stream is enabled.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
@param[in] number unsigned int16. Number of data words to transfer (65535 maximum).
@param[in] number unsigned int16. Number of data words to transfer (65535
maximum).
*/
void dma_set_number_of_data(u32 dma, u8 stream, u16 number)

18
lib/stm32/common/flash_common_f24.c
View File

@ -148,8 +148,7 @@ void flash_lock_option_bytes(void)
void flash_wait_for_last_operation(void)
{
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY)
;
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY);
}
void flash_program_double_word(u32 address, u64 data)
@ -218,13 +217,15 @@ void flash_program_byte(u32 address, u8 data)
FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_program(u32 address, u8* data, u32 len)
void flash_program(u32 address, u8 *data, u32 len)
{
/* TODO: Use dword and word size program operations where possible for turbo
* speed. */
/* TODO: Use dword and word size program operations where possible for
* turbo speed.
*/
u32 i;
for (i=0; i<len; i++)
for (i = 0; i < len; i++) {
flash_program_byte(address+i, data[i]);
}
}
void flash_erase_sector(u8 sector, u32 program_size)
@ -258,10 +259,11 @@ void flash_program_option_bytes(u32 data)
{
flash_wait_for_last_operation();
if (FLASH_OPTCR & FLASH_OPTCR_OPTLOCK)
if (FLASH_OPTCR & FLASH_OPTCR_OPTLOCK) {
flash_unlock_option_bytes();
}
FLASH_OPTCR = data & ~0x3;
FLASH_OPTCR |= FLASH_OPTCR_OPTSTRT; /* Enable option byte programming. */
FLASH_OPTCR |= FLASH_OPTCR_OPTSTRT; /* Enable option byte prog. */
flash_wait_for_last_operation();
}

44
lib/stm32/common/gpio_common_all.c
View File

@ -23,69 +23,73 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#define WEAK __attribute__ ((weak))
#define WEAK __attribute__((weak))
#include <libopencm3/stm32/gpio.h>
/**@{*/
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Set a Group of Pins Atomic
Set one or more pins of the given GPIO port to 1 in an atomic operation.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
If multiple pins are to be changed, use logical OR '|' to separate them.
If multiple pins are to be changed, use logical OR '|' to separate
them.
*/
void gpio_set(u32 gpioport, u16 gpios)
{
GPIO_BSRR(gpioport) = gpios;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Clear a Group of Pins Atomic
Clear one or more pins of the given GPIO port to 0 in an atomic operation.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
If multiple pins are to be changed, use logical OR '|' to separate them.
If multiple pins are to be changed, use logical OR '|' to separate
them.
*/
void gpio_clear(u32 gpioport, u16 gpios)
{
GPIO_BSRR(gpioport) = (gpios << 16);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Read a Group of Pins.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
If multiple pins are to be read, use logical OR '|' to separate them.
@return Unsigned int16 value of the pin values. The bit position of the pin value
returned corresponds to the pin number.
If multiple pins are to be read, use logical OR '|' to separate
them.
@return Unsigned int16 value of the pin values. The bit position of the pin
value returned corresponds to the pin number.
*/
u16 gpio_get(u32 gpioport, u16 gpios)
{
return gpio_port_read(gpioport) & gpios;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Toggle a Group of Pins
Toggle one or more pins of the given GPIO port. This is not an atomic operation.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
If multiple pins are to be changed, use logical OR '|' to separate them.
If multiple pins are to be changed, use logical OR '|' to separate
them.
*/
void gpio_toggle(u32 gpioport, u16 gpios)
{
GPIO_ODR(gpioport) ^= gpios;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Read from a Port
Read the current value of the given GPIO port. Only the lower 16 bits contain
@ -99,7 +103,7 @@ u16 gpio_port_read(u32 gpioport)
return (u16)GPIO_IDR(gpioport);
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Write to a Port
Write a value to the given GPIO port.
@ -112,15 +116,17 @@ void gpio_port_write(u32 gpioport, u16 data)
GPIO_ODR(gpioport) = data;
}
/*-----------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/** @brief Lock the Configuration of a Group of Pins
The configuration of one or more pins of the given GPIO port is locked. There is
no mechanism to unlock these via software. Unlocking occurs at the next reset.
The configuration of one or more pins of the given GPIO port is locked. There
is no mechanism to unlock these via software. Unlocking occurs at the next
reset.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
If multiple pins are to be locked, use logical OR '|' to separate them.
If multiple pins are to be locked, use logical OR '|' to separate
them.
*/
void gpio_port_config_lock(u32 gpioport, u16 gpios)
{
@ -133,7 +139,9 @@ void gpio_port_config_lock(u32 gpioport, u16 gpios)
reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */
reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */
/* Tell the compiler the variable is actually used. It will get optimized out anyways. */
/* Tell the compiler the variable is actually used. It will get
* optimized out anyways.
*/
reg32 = reg32;
/* If (reg32 & GPIO_LCKK) is true, the lock is now active. */

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